Difference between revisions of "MX8M GPIO"

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(Created page with "{{PageHeader|DART-MX8M- GPIO}} {{DocImage|category1=DART-MX8M|category2=Yocto}} __toc__ = GPIO state = The current state of the system's GPIOs can be obtained in user-mode, a...")
 
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<pre>
 
<pre>
 
root@imx8m-var-dart:~# cat /sys/kernel/debug/gpio
 
root@imx8m-var-dart:~# cat /sys/kernel/debug/gpio
GPIOs 0-31, platform/209c000.gpio, 209c000.gpio:
+
gpiochip0: GPIOs 0-31, parent: platform/30200000.gpio, 30200000.gpio:
  gpio-10 (phy-reset          ) out lo    
+
  gpio-8  (                    |eth_phy_pwr        ) out hi   
 +
  gpio-9  (                   |phy-reset          ) out hi    
 +
gpio-10  (                    |connect            ) in  hi IRQ
  
GPIOs 32-63, platform/20a0000.gpio, 20a0000.gpio:
+
gpiochip1: GPIOs 32-63, parent: platform/30210000.gpio, 30210000.gpio:
 +
gpio-44  (                    |cd                  ) in  lo IRQ
 +
gpio-51  (                    |VSD_3V3            ) out hi   
  
GPIOs 64-95, platform/20a4000.gpio, 20a4000.gpio:
+
gpiochip2: GPIOs 64-95, parent: platform/30220000.gpio, 30220000.gpio:
gpio-68  (ft5x06_irq_gpio    ) in  hi   
 
  
GPIOs 96-127, platform/20a8000.gpio, 20a8000.gpio:
+
gpiochip3: GPIOs 96-127, parent: platform/30230000.gpio, 30230000.gpio:
  gpio-115 (2190000.usdhc cd    ) in  hi  
+
  gpio-102 (                    |Back                ) in  hi IRQ
  gpio-116 (IDE Activity        ) out lo   
+
gpio-109 (                   |Home                ) in  hi IRQ
  gpio-117 (Heart Beat          ) out lo     
+
  gpio-111 (                   |Down                ) in  hi IRQ
 
+
  gpio-113 (                   |?                  ) out lo     
GPIOs 128-159, platform/20ac000.gpio, 20ac000.gpio:
+
  gpio-114 (                   |Up                  ) in  hi IRQ
  gpio-128 (phy-reset          ) out lo
 
 
</pre>
 
</pre>
  
 
Each GPIO is defined as in or out and the state is shown as lo or hi.<br>
 
Each GPIO is defined as in or out and the state is shown as lo or hi.<br>
For example pin 115 is the SD card card-detect.
+
For example pin 44 is the SD card card-detect.
 
When an SD card is plugged in, the state will be:
 
When an SD card is plugged in, the state will be:
 
<pre>
 
<pre>
  gpio-115 (2190000.usdhc cd   ) in  lo
+
  gpio-44  (                   |cd                 ) in  lo IRQ
 
</pre>
 
</pre>
 
When the SD card is removed, the state will be:
 
When the SD card is removed, the state will be:
 
<pre>
 
<pre>
  gpio-115 (2190000.usdhc cd   ) in  hi
+
  gpio-44  (                   |cd                 ) in  hi IRQ
 
</pre>
 
</pre>
  
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</pre>
 
</pre>
 
Adding only the one with the GPIO4_IO2 suffix (function) to your dts file will let you use the pin as GPIO.
 
Adding only the one with the GPIO4_IO2 suffix (function) to your dts file will let you use the pin as GPIO.
 
=== Variscite dts files ===
 
{| class="wikitable"
 
|-
 
! scope="col" | Device Tree Name<br/>
 
! scope="col" | SOM type<br/>
 
! scope="col" | CPU type<br/>
 
! scope="col" | Carrier Board type<br/>
 
! scope="col" | LCD Type<br/>
 
! scope="col" | Evaluation Kit name<br/>
 
|-
 
| imx6ul-var-dart.dtsi
 
| DART-6UL
 
| iMX6UL
 
| VAR-6ULCustomBoard
 
| Capacitive/ touch
 
|VAR-STK-6UL<br/>VAR-DVK-6UL
 
|-
 
| imx6ull-var-dart.dtsi
 
| DART-6UL
 
| iMX6ULL
 
| VAR-6ULCustomBoard
 
| Capacitive/ touch
 
|VAR-STK-6UL<br/>VAR-DVK-6UL
 
|-
 
| imx6ul-imx6ull-var-dart-common.dtsi
 
| DART-6UL
 
| iMX6UL/iMX6ULL
 
| VAR-6ULCustomBoard
 
| Capacitive/ touch
 
|VAR-STK-6UL<br/>VAR-DVK-6UL
 
|-
 
|}
 
For example, imx6ul-var-dart.dtsi starts with definitions and including dtsi files.
 
<pre>
 
#include <dt-bindings/input/input.h>
 
#include "imx6ul.dtsi"
 
</pre>
 
<br/>
 
The imx6ul.dtsi define the CPU platform and which pinfunc file will be included. This feature allow the pin name to be agnostic to the CPU type (i.MX6Q vs i.MX6DL)
 
<br/>
 
We create 8 DTB's out of imx6ul-imx6ull-var-dart-common.dtsi.
 
Variscite defines dts file for each platform.
 
<pre>
 
imx6ul-var-dart-nand_wifi.dts
 
imx6ul-var-dart-sd_nand.dts
 
imx6ul-var-dart-emmc_wifi.dts
 
imx6ul-var-dart-sd_emmc.dts
 
 
imx6ull-var-dart-nand_wifi.dts
 
imx6ull-var-dart-sd_nand.dts
 
imx6ull-var-dart-emmc_wifi.dts
 
imx6ull-var-dart-sd_emmc.dts
 
</pre>
 
They just define one of
 
<pre>
 
/* #define WIFI */
 
/* #define EMMC */
 
/* #define  NAND  */
 
</pre>
 
The WIFI and SCDARD share the same MMC interface. So only one of them can be activated at a time.
 
The NAND and eMMC share the same interface I/O. So only one of them can be activated at a time.
 
  
 
== Define a pin as GPIO in the kernel Device Tree ==
 
== Define a pin as GPIO in the kernel Device Tree ==
 
You need to add the relevant definitions to your device tree, as explained in the [[#Pin Func files|Pin Func files]] section above.<br>
 
You need to add the relevant definitions to your device tree, as explained in the [[#Pin Func files|Pin Func files]] section above.<br>
Edit arch/arm/boot/dts/imx6ul-var-dart.dts and add the definition for the GPIO you need in the section below.<br>
+
Edit arch/arm64/boot/dts/variscite/imx8m-var-dart-common.dtsi and add the definition for the GPIO you need in the iomuxc node.<br>
 
<pre>
 
<pre>
 +
&iomuxc {
 
pinctrl-names = "default";
 
pinctrl-names = "default";
 
pinctrl-0 = <&pinctrl_hog>;
 
pinctrl-0 = <&pinctrl_hog>;
  
pinctrl-0 = <&pinctrl_hog_1>;
+
imx8mq-evk {
imx6ul-evk {
+
pinctrl_hog: hoggrp {
pinctrl_hog_1: hoggrp-1 {
 
 
fsl,pins = <
 
fsl,pins = <
MX6UL_PAD_CSI_HSYNC__GPIO4_IO20 0x1b0b0 /* Led 1 */
+
/* Add your GPIO definitions here */  
MX6UL_PAD_CSI_DATA00__GPIO4_IO21 0x1b0b0 /* Led 2 */
 
MX6UL_PAD_GPIO1_IO00__GPIO1_IO00 0x17059 /* User Button */
 
MX6UL_PAD_GPIO1_IO07__ENET2_MDC 0x1b0b0
 
MX6UL_PAD_GPIO1_IO06__ENET2_MDIO 0x1b0b0
 
MX6UL_PAD_SNVS_TAMPER4__GPIO5_IO04 0x1b0b0 /* BT Enable */
 
 
>;
 
>;
 
};
 
};
 +
};
 +
...
 +
};
 +
 
</pre>
 
</pre>
  

Revision as of 10:11, 8 July 2018

DART-MX8M- GPIO

1 GPIO state

The current state of the system's GPIOs can be obtained in user-mode, as shown in the following example:

root@imx8m-var-dart:~# cat /sys/kernel/debug/gpio
gpiochip0: GPIOs 0-31, parent: platform/30200000.gpio, 30200000.gpio:
 gpio-8   (                    |eth_phy_pwr         ) out hi    
 gpio-9   (                    |phy-reset           ) out hi    
 gpio-10  (                    |connect             ) in  hi IRQ

gpiochip1: GPIOs 32-63, parent: platform/30210000.gpio, 30210000.gpio:
 gpio-44  (                    |cd                  ) in  lo IRQ
 gpio-51  (                    |VSD_3V3             ) out hi    

gpiochip2: GPIOs 64-95, parent: platform/30220000.gpio, 30220000.gpio:

gpiochip3: GPIOs 96-127, parent: platform/30230000.gpio, 30230000.gpio:
 gpio-102 (                    |Back                ) in  hi IRQ
 gpio-109 (                    |Home                ) in  hi IRQ
 gpio-111 (                    |Down                ) in  hi IRQ
 gpio-113 (                    |?                   ) out lo    
 gpio-114 (                    |Up                  ) in  hi IRQ

Each GPIO is defined as in or out and the state is shown as lo or hi.
For example pin 44 is the SD card card-detect. When an SD card is plugged in, the state will be:

 gpio-44  (                    |cd                  ) in  lo IRQ

When the SD card is removed, the state will be:

 gpio-44  (                    |cd                  ) in  hi IRQ

2 Manipulating a single GPIO via /sys/class/gpio

2.1 Using a command line or a script

GPIOs in i.MX are grouped in groups of 32 pins.
For example, GPIO1_3 belong to the first group, pin 3. Its absolute number will be 3.
GPIO4_21 will be (4-1)*32+21=117.
Assuming this GPIO is defined in your device tree, the following is an example of how to use it from userspace.

To export the GPIO for userspace use:

$ echo 117 > /sys/class/gpio/export


To configure as output:

$ echo out > /sys/class/gpio/gpio117/direction

Set GPIO high:

$ echo 1 > /sys/class/gpio/gpio117/value

Set GPIO low:

$ echo 0 > /sys/class/gpio/gpio117/value


To configure as input:

$ echo in > /sys/class/gpio/gpio117/direction

Read the current value:

$ cat /sys/class/gpio/gpio117/value


To free the GPIO after you're done using it:

$ echo 117 > /sys/class/gpio/unexport

2.2 Using a C application

All of the command line operations above can be translated to C code:
Reserve (export) the GPIO:

#define IMX_GPIO_NR(port, index)    ((((port)-1)*32)+((index)&31))

int fd;
char buf[MAX_BUF]; 
int gpio = IMX_GPIO_NR(4, 21); /* Just an example */

fd = open("/sys/class/gpio/export", O_WRONLY);

sprintf(buf, "%d", gpio); 

write(fd, buf, strlen(buf));

close(fd);

Set the GPIO direction:

sprintf(buf, "/sys/class/gpio/gpio%d/direction", gpio);

fd = open(buf, O_WRONLY);

/* Set out direction */
write(fd, "out", 3); 
/* Set in direction */
write(fd, "in", 2); 

close(fd);

In case of out direction set the GPIO value:

sprintf(buf, "/sys/class/gpio/gpio%d/value", gpio);

fd = open(buf, O_WRONLY);

/* Set GPIO high status */
write(fd, "1", 1); 
/* Set GPIO low status */
write(fd, "0", 1); 

close(fd);

In case of in direction get the current GPIO value:

char value;

sprintf(buf, "/sys/class/gpio/gpio%d/value", gpio);

fd = open(buf, O_RDONLY);

read(fd, &value, 1);

if (value == '0') { 
     /* Current GPIO status low */
} else {
     /* Current GPIO status high */
}

close(fd);

Once finished, free (unexport) the GPIO:

fd = open("/sys/class/gpio/unexport", O_WRONLY);

sprintf(buf, "%d", gpio);

write(fd, buf, strlen(buf));

close(fd);

Important notes:

  • Remember that after the first read operation the file pointer will move to the next position in the file, so to get a correct value for each read operation you simply have to set the file pointer at the beginning of the file before read by using the following command:
lseek(fd, 0, SEEK_SET);
  • This is only a short example. If you want to use it in your code remember add error handling to it.

3 Kernel Device Tree GPIO configuration

3.1 Device Tree GPIO files

3.1.1 Pin Func files

In the directory include/dt-bindings/pinctrl/ of the Linux kernel source you will find the pin functions definition files.
The relevant file is pins-imx8mq.h.
If you search it for GPIO4_IO2, for example, you will see a group of definitions with same prefix (pad name), "MX8MQ_IOMUXC_SAI1_RXD0".

#define MX8MQ_IOMUXC_SAI1_RXD0_SAI1_RX_DATA0                                0x164 0x3CC 0x000 0x0 0x0
#define MX8MQ_IOMUXC_SAI1_RXD0_SAI5_RX_DATA0                                0x164 0x3CC 0x4D4 0x1 0x1
#define MX8MQ_IOMUXC_SAI1_RXD0_CORESIGHT_TRACE0                             0x164 0x3CC 0x000 0x4 0x0
#define MX8MQ_IOMUXC_SAI1_RXD0_GPIO4_IO2                                    0x164 0x3CC 0x000 0x5 0x0
#define MX8MQ_IOMUXC_SAI1_RXD0_CCMSRCGPCMIX_BOOT_CFG0                       0x164 0x3CC 0x000 0x6 0x0
#define MX8MQ_IOMUXC_SAI1_RXD0_SIM_M_HADDR17                                0x164 0x3CC 0x000 0x7 0x0

Adding only the one with the GPIO4_IO2 suffix (function) to your dts file will let you use the pin as GPIO.

3.2 Define a pin as GPIO in the kernel Device Tree

You need to add the relevant definitions to your device tree, as explained in the Pin Func files section above.
Edit arch/arm64/boot/dts/variscite/imx8m-var-dart-common.dtsi and add the definition for the GPIO you need in the iomuxc node.

&iomuxc {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_hog>;

	imx8mq-evk {
		pinctrl_hog: hoggrp {
			fsl,pins = <
				/* Add your GPIO definitions here */ 
			>;
		};
	};
 ...
};

3.2.1 Device Tree GPIO attribute

If you look at Documentation/devicetree/bindings/pinctrl/fsl,imx6ul-pinctrl.txt in the Linux kernel source tree, the number to the right of the pin control spec can be used for additional attributes like pull-ups, pull-downs, keepers, drive strength, etc.
The value 0x80000000 is "don't know value please use the default". Else use the table below to set it to the required value.

CONFIG bits definition
value
PAD_CTL_HYS (1 << 16)
PAD_CTL_PUS_100K_DOWN (0 << 14)
PAD_CTL_PUS_47K_UP (1 << 14)
PAD_CTL_PUS_100K_UP (2 << 14)
PAD_CTL_PUS_22K_UP (3 << 14)
PAD_CTL_PUE (1 << 13)
PAD_CTL_PKE (1 << 12)
PAD_CTL_ODE (1 << 11)
PAD_CTL_SPEED_LOW (1 << 6)
PAD_CTL_SPEED_MED (2 << 6)
PAD_CTL_SPEED_HIGH (3 << 6)
PAD_CTL_DSE_DISABLE (0 << 3)
PAD_CTL_DSE_240ohm (1 << 3)
PAD_CTL_DSE_120ohm (2 << 3)
PAD_CTL_DSE_80ohm (3 << 3)
PAD_CTL_DSE_60ohm (4 << 3)
PAD_CTL_DSE_48ohm (5 << 3)
PAD_CTL_DSE_40ohm (6 << 3)
PAD_CTL_DSE_34ohm (7 << 3)
PAD_CTL_SRE_FAST (1 << 0)
PAD_CTL_SRE_SLOW (0 << 0)