DART-MX8M SPI
This page is using the default release RELEASE_SUMO_V1.0_DART-MX8M.
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In this example we will show how to configure and test SPI1 on DART-MX8M. The SPI pins on external connector J16
are used for SPI loopback test.
1 Kernel configuration
Verify that the i.MX SPI driver (CONFIG_SPI_IMX) is enabled in your kernel configuration:
- In menuconfig: Device Drivers -> SPI support -> <*> Freescale i.MX SPI controllers
Verify that the User mode SPI driver (CONFIG_SPI_SPIDEV) is enabled in your kernel configuration:
- In menuconfig: Device Drivers -> SPI support -> <*> User mode SPI device driver support
2 Device Tree configuration
The default DART-MX8M SPI configuration is for resistive touch controller on CS0. For the purpose of loop back test the configuration should be modified to use a different CS line.
2.1 Add spidev node
Edit arch/arm64/boot/dts/freescale/fsl-imx8mq-var-dart-common.dtsi to modify cs-gpios property and add spidev node.
GPIO1_12 will be used in this example to control SPI CS0.
&ecspi1 { #address-cells = <1>; #size-cells = <0>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_ecspi1>; cs-gpios = <&gpio1 12 0>; fsl,spi-num-chipselects = <1>; status = "okay"; spidev@0 { compatible = "spidev"; spi-max-frequency = <12000000>; reg = <0>; }; };
2.2 Configure SPI1 pins
&iomuxc { imx8m-var-dart { ... pinctrl_ecspi1: ecspi1grp { fsl,pins = < MX8MQ_IOMUXC_ECSPI1_SCLK_ECSPI1_SCLK 0x11 MX8MQ_IOMUXC_ECSPI1_MOSI_ECSPI1_MOSI 0x11 MX8MQ_IOMUXC_ECSPI1_MISO_ECSPI1_MISO 0x11 MX8MQ_IOMUXC_ECSPI1_SS0_GPIO5_IO9 0x11 MX8MQ_IOMUXC_GPIO1_IO12_GPIO1_IO12 0x11 >; }; ... }; };
3 Recompile the kernel
Compile the kernel (only if kernel configuration was changed) and device tree and update the SOM.
4 Compile SPI test application
There's an SPI test utility in the kernel source tree: tools/spi/spidev_test.c
To cross compile it, use the following command:
$ $CC ./tools/spi/spidev_test.c -o ./spidev_test
4.1 SPI 1 External Connector
SPI 1 will be accessible on the following EVK pins:
- J16.2 - SPI1.SCLK
- J16.4 - SPI1.SS0
- J16.6 - SPI1.MOSI
- J16.8 - SPI1.MISO
5 Run SPI Test
Copy spidev_test binary to DART-MX8M.
Loop SPI1.MOSI and SPI1.MISO by putting a jumper on J16.6 and J16.8
Configure GPIO5_9 (the default CS0 pin) as output with value 1 to prevent it from interfering with new CS0 pin
# echo 137 > /sys/class/gpio/export # echo out > /sys/class/gpio/gpio137/direction # echo 1 > /sys/class/gpio/gpio137/value
Run SPI test tool
# ./spidev_test -v -D /dev/spidev0.0
The output of successful test should look like this:
spi mode: 0x20 bits per word: 8 max speed: 500000 Hz (500 KHz) TX | FF FF FF FF FF FF 40 00 00 00 00 95 FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF F0 0D | ......@....�..................�. RX | FF FF FF FF FF FF 40 00 00 00 00 95 FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF F0 0D | ......@....�..................�.
6 Using multiple SPI CS lines
The i.MX8M SPI controllers support up to 4 chip select lines.
In the example below GPIO1_12 and GPIO1_15 are used to control CS0 and CS1 respectively.
When selecting CS GPIO pins make sure they are not used to control other peripherals.
&ecspi1 { #address-cells = <1>; #size-cells = <0>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_ecspi1>; cs-gpios = <&gpio1 12 0>, <&gpio1 15 0>; fsl,spi-num-chipselects = <2>; status = "okay"; chip1@0 { reg = <0>; ... }; chip2@1 { reg = <1>; ... }; };
&iomuxc { imx8m-var-dart { ... pinctrl_ecspi1: ecspi1grp { fsl,pins = < MX8MQ_IOMUXC_ECSPI1_SCLK_ECSPI1_SCLK 0x11 MX8MQ_IOMUXC_ECSPI1_MOSI_ECSPI1_MOSI 0x11 MX8MQ_IOMUXC_ECSPI1_MISO_ECSPI1_MISO 0x11 MX8MQ_IOMUXC_GPIO1_IO12_GPIO1_IO12 0x11 MX8MQ_IOMUXC_GPIO1_I015_GPIO1_IO15 0x11 >; }; ... }; };