From Variscite Wiki
Revision as of 09:56, 8 August 2021 by Eran (talk | contribs)
(diff) ← Older revision | Latest revision (diff) | Newer revision → (diff)

The iMX6UL/ULL SoC supports up to 10 ADC input channels signals of 12 bit resolution, right-justified unsigned format. The ADC input channels are available on CPU pads GPIO1_IO00 to GPIO1_IO09.

1 Example: Configuring ADC channels 5,9

1.1 Changes needed in "imx6ul.dtsi"

The ADC interface is defined in the In the kernel source code, arch/arm/boot/dts/imx6ul.dtsi file

adc1: adc@02198000 {
	compatible = "fsl,imx6ul-adc", "fsl,vf610-adc";
	reg = <0x02198000 0x4000>;
	interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&clks IMX6UL_CLK_ADC1>;
	num-channels = <2>;
	clock-names = "adc";
	status = "disabled";

Edit the imx6ul.dtsi file and add the following adc1 alias to the aliases node:

aliases {
	adc1 = &adc1;

1.2 Changes needed in "imx6ul-imx6ull-var-dart.dtsi" / "imx6ul-imx6ull-var-som.dtsi"

The ADC channel mapping is consecutive i.e. GPIO1_IO00 to GPIO1_IO09 pads, correspond to ADC inputs 0 to 9. Enabling the the ADC mode does not prevent the usage of these pads as GPIOs.
Add the below section:

&adc1 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_adc1>;
	vref-supply = <&touch_3v3_regulator>;
	num-channels = <10>;
	status = "okay";

Add the pinctrl_adc1 definition under &iomuxc section setting these pads as GPIOs.
Note: Make sure to remove/disable occurrences of these pins if they are used in other sections in the device tree file.
For using GPIO1_IO05 on VAR-SOM-6UL, please disable &pwm section in "imx6ul-imx6ull-var-som-concerto-board.dtsi" / "imx6ul-imx6ull-var-som-symphony-board.dtsi" files.

&iomuxc {
	pinctrl_adc1: adc1grp {
		fsl,pins = <
			MX6UL_PAD_GPIO1_IO05__GPIO1_IO05 0xb0
			MX6UL_PAD_GPIO1_IO09__GPIO1_IO09 0xb0

'num-channels' values range from 1 to 10, ADC channels range from 0 to 9. 'num-channels' value should be number of highest ADC channel you will be using +1 .
If you wish to define only specific ADC pads and set the number of channels accordingly, the ADC driver "vf610_adc.c" should be modified (https://github.com/varigit/linux-imx/blob/lf-5.4.y_var01/drivers/iio/adc/vf610_adc.c#L527).
In "static const struct iio_chan_spec vf610_adc_iio_channels[]" change order of the channels as below:

static const struct iio_chan_spec vf610_adc_iio_channels[] = {
	/*  remaining channels*/

Then you can set in &adc1 "num-channels = <2>"

2 Testing the ADC

A file named "in_voltageX_raw" is created for each ADC channel, under /sys/bus/iio/devices/iio:device0.
To view all available ADC channels files created under the sysfs:

root@imx6ul-var-dart:~# cd /sys/bus/iio/devices/iio:device0
root@imx6ul-var-dart:/sys/bus/iio/devices/iio:device0# ls *in_voltage*_raw
in_voltage0_raw  in_voltage3_raw  in_voltage6_raw  in_voltage9_raw
in_voltage1_raw  in_voltage4_raw  in_voltage7_raw
in_voltage2_raw  in_voltage5_raw  in_voltage8_raw

2.1 Reading ADC input value

On DART-6ULCustomBoard, GPIO1_IO05, GPIO1_IO09 are exported on J8.1, J8.3 respectively. GND (0V) , 3.3V are exported on J6.8 , J6.9 respectively.

On Concerto-Board, GPIO1_IO05, GPIO1_IO09 are exported on J20.19 , J26.6 respectively. GND (0V) , 3.3V are exported on J26.20 , J26.18 respectively.

Short GPIO1_IO05, GPIO1_IO09 to GND and read value:

root@imx6ul-var-dart:/sys/bus/iio/devices/iio:device0# cat in_voltage5_raw
root@imx6ul-var-dart:/sys/bus/iio/devices/iio:device0# cat in_voltage9_raw

Short GPIO1_IO05, GPIO1_IO09 to 3.3V and read value:

root@imx6ul-var-dart:/sys/bus/iio/devices/iio:device0# cat in_voltage5_raw
root@imx6ul-var-dart:/sys/bus/iio/devices/iio:device0# cat in_voltage9_raw

2.2 ADC input voltage calculation

The ADC input voltage (Vin) can be calculated according to the following formula:
Vin = Vref* (Vread/4095)


  • Vread is the digital value reading
  • Vref is the ADC voltage reference which is set to 3.3V on SOM