VAR-SOM-MX93 SPI

In this example we will show how to configure and test SPI1 on VAR-SOM-MX93. The SPI pins on external connector J16 are used for SPI loopback test.

Kernel configuration

Verify that the i.MX SPI driver (CONFIG_SPI_IMX) is enabled in your kernel configuration:

In menuconfig: Device Drivers -> SPI support -> <*> Freescale i.MX SPI controllers

Verify that the User mode SPI driver (CONFIG_SPI_SPIDEV) is enabled in your kernel configuration:

In menuconfig: Device Drivers -> SPI support -> <*> User mode SPI device driver support

Device Tree configuration

On the VAR-SOM-MX93, lpspi6 is configured with a spidev device that can be used to test SPI. The following steps demonstrate how to test spidev.

Add spidev node

Edit /arch/arm64/boot/dts/freescale/imx93-var-som-symphony.dts to modify cs-gpios property and add spidev node.
GPIO2_0 will be used in this example to control SPI CS0.

&lpspi6 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_lpspi6>;
	cs-gpios = <&gpio2 0 GPIO_ACTIVE_LOW>;
	status = "okay";

	/* Test SPI device */
	spidev@0 {
		reg = <0>;
		compatible = "var,spidev";
		spi-max-frequency = <1000000>;
		status = "okay";
	};
};

Configure SPI1 pins

&iomuxc {
		...
		pinctrl_lpspi6: lpspi6grp {
			fsl,pins = <
				MX93_PAD_GPIO_IO00__GPIO2_IO00		0x31e
				MX93_PAD_GPIO_IO01__LPSPI6_SIN		0x31e
				MX93_PAD_GPIO_IO02__LPSPI6_SOUT		0x31e
				MX93_PAD_GPIO_IO03__LPSPI6_SCK	        0x31e
			>;
		};
		...
};

Recompile the kernel

Compile the kernel (only if kernel configuration was changed) and device tree and update the SOM.

Compile SPI test application

There's an SPI test utility in the kernel source tree: tools/spi/spidev_test.c
To cross compile it, use the following command:

$ $CC ./tools/spi/spidev_test.c -o ./spidev_test

SPI 1 External Connector

SPI 1 will be accessible on the following EVK pins:

J16.2 - SPI1.SCLK
J16.4 - SPI1.SS0
J16.6 - SPI1.MOSI
J16.8 - SPI1.MISO

Run SPI Test

Copy spidev_test binary to DART-MX8M.
Loop SPI1.MOSI and SPI1.MISO by putting a jumper on J16.6 and J16.8

Run SPI test tool

# ./spidev_test -v -D /dev/spidev0.0

The output of successful test should look like this:

spi mode: 0x20
bits per word: 8
max speed: 500000 Hz (500 KHz)
TX | FF FF FF FF FF FF 40 00 00 00 00 95 FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF F0 0D  | ......@....�..................�.
RX | FF FF FF FF FF FF 40 00 00 00 00 95 FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF F0 0D  | ......@....�..................�.

Using multiple SPI CS lines

The i.MX9 SPI controllers support up to 2 chip select lines.
In the example below GPIO1_12 and GPIO1_15 are used to control CS0 and CS1 respectively.
When selecting CS GPIO pins make sure they are not used to control other peripherals.

&ecspi1 {
	#address-cells = <1>;
	#size-cells = <0>;
 	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_ecspi1>;
        cs-gpios = <&gpio1 12 0>,
                   <&gpio1 15 0>;
        fsl,spi-num-chipselects = <2>;
	status = "okay";

        chip1@0 {
               reg = <0>;
               ...
        };

        chip2@1 {
               reg = <1>;
               ...
        };
};

DART-MX8M SPI

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