VAR-SOM-MX93 Display
Introduction
Display Interfaces
The i.MX 93 SoC includes one instance of LCDIF. One LCDIF can drive any of three displays or drive the same output to multiple displays:
- MIPI DSI 4-lane (up to 1920x1200p60)
- LVDS Bridge (LDB) (up to 1366x768p60 or 1280x800p60)
- Parallel Display
Adding custom LVDS panel
VAR-SOM-MX93 evaluation kit comes with 800x480 LCD panel. VAR-SOM-MX93 DTS file was created with this panel in mind. To support your custom LVDS panel, you should make several modifications
Referencing custom panel in the DTS file
The following code references Variscite panel in arch/arm64/boot/dts/freescale/imx93-var-som-symphony.dts under kernel source tree
lvds_panel {
compatible = "sgd,gktw70sdae4se", "panel-lvds";
backlight = <&backlight>;
width-mm = <153>;
height-mm = <87>;
label = "gktw70sdae4se";
data-mapping = "jeida-24";
status = "okay";
/*
* Timings according to VLCD-CAP-GLD-LVDS datasheet.
* pixel clock required: typ. 30 Mhz, max. 40 MHz
* video PLL clock: 498 MHz (see lcdif node)
* pixel clock: 498000000 Hz / 7 / 2 = 35571429 Hz
*/
panel-timing {
clock-frequency = <35571429>;
hactive = <800>;
vactive = <480>;
hback-porch = <40>;
hfront-porch = <40>;
vback-porch = <29>;
vfront-porch = <13>;
hsync-len = <48>;
vsync-len = <3>;
hsync-active = <0>;
vsync-active = <0>;
de-active = <1>;
};
...
};
You should modify the "data-mapping" and "panel-timings" properties to match your panel specification and rebuild the DTB file.
Known issues and limitations
The i.MX93 uses a hierarchical clock system to generate the required pixel clock for LVDS output. This system is centered around the Video PLL (pll_video) and a series of integer dividers used to derive precise clock frequencies for the display interfaces. Divisors are 8-bit integers, supporting a maximum division factor of 256 (CLOCK_ROOTn_CONTROL[DIV]+1).
In the following, the relevant clocks are shown:
video_pll ├── media_ldb_root └── media_disp_pix_root
Where media_disp_pix_root is the LVDS clock and is always given by media_ldb_root / 7. The video_pll clock, the parent clock, is specified within the lcdif device tree node (see arch/arm64/boot/dts/freescale/imx93-var-som-symphony.dts) and supports only pre-defined setpoints defined in the associated kernel driver.
The LVDS clock frequency, given by the property clock-frequency in the panel node, is computed by the clock subsystem as close as possible according to the described clock architecture. For example, with the given video_pll of 498 MHz, the following pixel clock frequencies are achievable:
70 MHz: media_disp_pix_root: 71142857 Hz
30 MHz: media_disp_pix_root: 35571429 Hz
20 MHz: media_disp_pix_root: 23714286 Hz
...
This can reasonably result in an approximated LVDS clock frequency generated, which may not fit the required LVDS timing specification. In this case, a PLL fine-tuning is required.
For example, let's assume the target LVDS clock should be 30 MHz. Based on the current clock settings, the LVDS clock frequency will be 35.57 MHz, giving an error of 18.57% compared to the desired value. Such an error might be too high the display system, resulting in misaligned content or even a black screen.
To overcome this issue, the video_pll root clock needs to be changed in a way that the clock subsystem can generate a closer clock. To change the video_pll root clock, the assigned-clock-rates property of the lcdif node in the device tree needs to be modified.
The current lcdif node implementation is shown in the following (see arch/arm64/boot/dts/freescale/imx93-var-som-symphony.dts).
&lcdif {
status = "okay";
assigned-clock-rates =
<498000000>, /* IMX93_CLK_VIDEO_PLL */
<71142857>, /* IMX93_CLK_MEDIA_DISP_PIX (IMX93_CLK_VIDEO_PLL / 7) */
<400000000>, /* IMX93_CLK_MEDIA_AXI */
<133333333>; /* IMX93_CLK_MEDIA_APB */
};
As already mentioned, the video_pll root clock only supports given setpoints pre-defined in the associated kernel driver. The available setpoints can be found in the kernel source code, see drivers/clk/imx/clk-fracn-gppll.c. For example, at the time, the available setpoints for the IMX93_CLK_VIDEO_PLL clock were:
/*
* Fvco = (Fref / rdiv) * (MFI + MFN / MFD)
* Fout = Fvco / odiv
* The (Fref / rdiv) should be in range 20MHz to 40MHz
* The Fvco should be in range 2.5Ghz to 5Ghz
*/
static const struct imx_fracn_gppll_rate_table fracn_tbl[] = {
PLL_FRACN_GP(1039500000U, 173, 25, 100, 1, 4),
PLL_FRACN_GP(650000000U, 162, 50, 100, 0, 6),
PLL_FRACN_GP(594000000U, 198, 0, 1, 0, 8),
PLL_FRACN_GP(560000000U, 140, 0, 1, 0, 6),
PLL_FRACN_GP(519750000U, 173, 25, 100, 1, 8),
PLL_FRACN_GP(498000000U, 166, 0, 1, 0, 8),
PLL_FRACN_GP(484000000U, 121, 0, 1, 0, 6),
PLL_FRACN_GP(445333333U, 167, 0, 1, 0, 9),
PLL_FRACN_GP(400000000U, 200, 0, 1, 0, 12),
PLL_FRACN_GP(393216000U, 163, 84, 100, 0, 10),
PLL_FRACN_GP(300000000U, 150, 0, 1, 0, 12)
};
To achieve the desired LVDS clock frequency the target value for media_ldb_root should be 30 MHz * 7 = 210 MHz. For simplicity, we will define video_pll equal to media_ldb_root (One can also consider the subsequent divisor of media_ldb_root, multiplying the target video_pll clock reasonably).
The table fracn_tbl provides pll_video setpoints with the following set of variables:
rate, mfi, mfn, mfd, rdiv, odiv
With the following formula:
Fvco = (Fref / rdiv) * (MFI + MFN / MFD) Fout = Fvco / odiv
Where Fref = 24 MHz (reference clock).
The value 210 MHz can be achieved with the following values:
Fvco = (24 MHz / 1) * (105 + 0 / 1) = 2520 MHz Fout = 2520 MHz / 12 = 210 MHz
Resulting in the following fracn_tbl table entry:
PLL_FRACN_GP(210000000U, 105, 0, 1, 0, 12)
Now we have to patch the kernel sources as follows:
- We need to add the PLL clock setpoint in the fracn_tbl table
- We need to update IMX93_CLK_VIDEO_PLL to 210000000 in the lcdif node to choose it (and update IMX93_CLK_MEDIA_DISP_PIX accordingly)
- We need to update the clock-frequency property to 30000000 in the panel node
After the changes, the clock subsystem should be able to set the LVDS clock as requested:
root@imx93-var-som:~# grep -e video_pll -e media_ldb_root -e media_disp_pix_root /sys/kernel/debug/clk/clk_summary
video_pll 2 2 0 210000000 0 0 50000 Y deviceless no_connection_id
media_disp_pix_root 2 2 0 30000000 0 0 50000 Y 4ae30000.lcd-controller pix
media_ldb_root 1 1 0 210000000 0 0 50000 Y deviceless no_connection_id
Rotating the Weston display
To rotate the Weston display, edit /etc/xdg/weston/weston.ini.
For example, rotate the display 90 degrees:
[output] name=LVDS-1 transform=rotate-90