VAR-SOM-MX6 UART
Test
By default, Variscite configured UART3 (ttymxc2).
To test it:
Use minicom to connect.
Set the serial to /dev/ttymxc2
You can use a loopback or connect to another computer
Example: configure UART4, ttymxc3
Note: The pins here are set arbitrarily. You should set them based on your hardware design, and make sure they are not conflicting with other devices in the device tree.
After applying tthe changes below, continue following the "Build Linux from source code" guide to build only the device trees and to copy them to your SD card.
VAR-SOM-SOLO / VAR-SOM-DUAL / VAR-SOM-MX6
Edit arch/arm/boot/dts/imx6qdl-var-som.dtsi
Look for:
/* ttymxc2 UART */ &uart3 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart3_2>; fsl,uart-has-rtscts; status = "okay"; };
Duplicate it and change the name and the pinctrl name.
For Example:
&uart4 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart4_1>; fsl,uart-has-rtscts; status = "okay"; };
Duplicate the corresponding pinctrl. Copy :
/* Variscite Uart3 support */ pinctrl_uart3_2: uart3grp-2 { /* RX/TX RTS/CTS */ fsl,pins = < MX6QDL_PAD_EIM_D25__UART3_RX_DATA 0x1b0b1 MX6QDL_PAD_EIM_D24__UART3_TX_DATA 0x1b0b1 MX6QDL_PAD_EIM_D23__UART3_CTS_B 0x1b0b1 MX6QDL_PAD_EIM_EB3__UART3_RTS_B 0x1b0b1 >; };
Into:
/* Variscite Uart4 support */ pinctrl_uart4_1: uart4grp-1 { /* RX/TX RTS/CTS */ fsl,pins = < MX6QDL_PAD_KEY_ROW0__UART4_RX_DATA 0x1b0b1 MX6QDL_PAD_KEY_COL0__UART4_TX_DATA 0x1b0b1 MX6QDL_PAD_CSI0_DAT16__UART4_RTS_B 0x1b0b1 MX6QDL_PAD_CSI0_DAT17__UART4_CTS_B 0x1b0b1 >; };
DART-MX6
Edit arch/arm/boot/dts/imx6qdl-var-dart.dtsi
Look for:
/* ttymxc2 UART */ &uart3 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart3_2>; fsl,uart-has-rtscts; status = "okay"; };
Duplicate it and change the name and the pinctrl name.
For Example:
&uart4 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart4_1>; status = "okay"; };
Duplicate the corresponding pinctrl. Copy :
/* Variscite Uart3 support */ pinctrl_uart3_2: uart3grp-2 { /* RX/TX RTS/CTS */ fsl,pins = < MX6QDL_PAD_EIM_D25__UART3_RX_DATA 0x1b0b1 MX6QDL_PAD_EIM_D24__UART3_TX_DATA 0x1b0b1 MX6QDL_PAD_EIM_D23__UART3_CTS_B 0x1b0b1 MX6QDL_PAD_EIM_EB3__UART3_RTS_B 0x1b0b1 >; };
Into:
/* Variscite Uart4 support */ pinctrl_uart4_1: uart4grp-1 { /* RX/TX */ fsl,pins = < MX6QDL_PAD_KEY_ROW0__UART4_RX_DATA 0x1b0b1 MX6QDL_PAD_KEY_COL0__UART4_TX_DATA 0x1b0b1 >; };
Configuring RS485 Half-Duplex
Each UART can be configured for RS485 Half-Duplex mode by using a GPIO pin to drive the receive and transmit enable inputs. This can be configured in the device tree by making the following changes to the uart node and replacing X, Y & Z with the proper values:
&uartX { /* Add RS485 properties to uartX */ pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uartX>, <&pinctrl_uartX_rs485>; /* Add RS485 GPIO pinctrl */ rts-gpios = <&gpioY Z GPIO_ACTIVE_LOW>; /* Add rts-gpios property */ linux,rs485-enabled-at-boot-time; /* Enable RS485 at boot time to skip using TIOCSRS485 ioctl */ status = "okay"; };
Next, configure the RS485 GPIO pin by adding pinctrl_uartX_rs485
to iomuxc
. Replace X, GPIO_PIN_FUNCTION, and GPIO_PIN_SETTINGS with the proper values:
&iomuxc { pinctrl_uartX_rs485: uartXrs485 { fsl,pins = < GPIO_PIN_FUNCTION GPIO_PIN_SETTINGS >; }; };
Note: For more information about configuring pins, please see i.MX Device Tree Pinmux Settings Guide
After making these changes, RS485 mode will be enabled by default and can be verified from the console by running the commands below. Replace N with the proper value, which is typically X-1 relative to the device tree node uartX
:
# stty -F /dev/ttymxcN -echo -onlcr 115200 # echo hello > /dev/ttymxcN
The below logic analyzer capture shows the RS485 RX/TX enable line toggling when writing to the UART:
Please refer to the Linux device tree bindings for more RS485 configuration options.