DART-6UL GPIO
GPIO state
The current state of the system's GPIOs can be obtained in user-mode, as shown in the following example:
root@imx6ul-var-dart:~# cat /sys/kernel/debug/gpio GPIOs 0-31, platform/209c000.gpio, 209c000.gpio: gpio-10 (phy-reset ) out lo GPIOs 32-63, platform/20a0000.gpio, 20a0000.gpio: GPIOs 64-95, platform/20a4000.gpio, 20a4000.gpio: gpio-68 (ft5x06_irq_gpio ) in hi GPIOs 96-127, platform/20a8000.gpio, 20a8000.gpio: gpio-115 (2190000.usdhc cd ) in hi gpio-116 (IDE Activity ) out lo gpio-117 (Heart Beat ) out lo GPIOs 128-159, platform/20ac000.gpio, 20ac000.gpio: gpio-128 (phy-reset ) out lo
Each GPIO is defined as in or out and the state is shown as lo or hi.
For example pin 115 is the SD card card-detect.
When an SD card is plugged in, the state will be:
gpio-115 (2190000.usdhc cd ) in lo
When the SD card is removed, the state will be:
gpio-115 (2190000.usdhc cd ) in hi
Manipulating a single GPIO via /sys/class/gpio
Using a command line or a script
GPIOs in i.MX are grouped in groups of 32 pins.
For example, GPIO1_3 belong to the first group, pin 3. Its absolute number will be 3.
GPIO4_21 will be (4-1)*32+21=117.
Assuming this GPIO is defined in your device tree, the following is an example of how to use it from userspace.
To export the GPIO for userspace use:
$ echo 117 > /sys/class/gpio/export
To configure as output:
$ echo out > /sys/class/gpio/gpio117/direction
Set GPIO high:
$ echo 1 > /sys/class/gpio/gpio117/value
Set GPIO low:
$ echo 0 > /sys/class/gpio/gpio117/value
To configure as input:
$ echo in > /sys/class/gpio/gpio117/direction
Read the current value:
$ cat /sys/class/gpio/gpio117/value
To free the GPIO after you're done using it:
$ echo 117 > /sys/class/gpio/unexport
Using a C application
All of the command line operations above can be translated to C code:
Reserve (export) the GPIO:
#define IMX_GPIO_NR(port, index) ((((port)-1)*32)+((index)&31))
int fd;
char buf[MAX_BUF];
int gpio = IMX_GPIO_NR(4, 21); /* Just an example */
fd = open("/sys/class/gpio/export", O_WRONLY);
sprintf(buf, "%d", gpio);
write(fd, buf, strlen(buf));
close(fd);
Set the GPIO direction:
sprintf(buf, "/sys/class/gpio/gpio%d/direction", gpio); fd = open(buf, O_WRONLY); /* Set out direction */ write(fd, "out", 3); /* Set in direction */ write(fd, "in", 2); close(fd);
In case of out direction set the GPIO value:
sprintf(buf, "/sys/class/gpio/gpio%d/value", gpio); fd = open(buf, O_WRONLY); /* Set GPIO high status */ write(fd, "1", 1); /* Set GPIO low status */ write(fd, "0", 1); close(fd);
In case of in direction get the current GPIO value:
char value;
sprintf(buf, "/sys/class/gpio/gpio%d/value", gpio);
fd = open(buf, O_RDONLY);
read(fd, &value, 1);
if (value == '0') {
/* Current GPIO status low */
} else {
/* Current GPIO status high */
}
close(fd);
Once finished, free (unexport) the GPIO:
fd = open("/sys/class/gpio/unexport", O_WRONLY);
sprintf(buf, "%d", gpio);
write(fd, buf, strlen(buf));
close(fd);
Important notes:
- Remember that after the first read operation the file pointer will move to the next position in the file, so to get a correct value for each read operation you simply have to set the file pointer at the beginning of the file before read by using the following command:
lseek(fd, 0, SEEK_SET);
- This is only a short example. If you want to use it in your code remember add error handling to it.
Kernel Device Tree GPIO configuration
Device Tree GPIO files
Pin Func files
In the directory arch/arm/boot/dts/ of the Linux kernel source you will find the pin functions definitions files.
The relevant file is imx6ul-pinfunc.h.
If you edit it and search for GPIO4_IO24, for example, you will see a group of definitions with same prefix (pad name), "MX6UL_PAD_CSI_DATA03".
#define MX6UL_PAD_CSI_DATA03__CSI_DATA05 0x01F0 0x047C 0x04CC 0 0 #define MX6UL_PAD_CSI_DATA03__USDHC2_DATA3 0x01F0 0x047C 0x0688 1 0 #define MX6UL_PAD_CSI_DATA03__SIM2_PORT1_PD 0x01F0 0x047C 0x0000 2 0 #define MX6UL_PAD_CSI_DATA03__ECSPI2_MISO 0x01F0 0x047C 0x0548 3 0 #define MX6UL_PAD_CSI_DATA03__EIM_AD03 0x01F0 0x047C 0x0000 4 0 #define MX6UL_PAD_CSI_DATA03__GPIO4_IO24 0x01F0 0x047C 0x0000 5 0 #define MX6UL_PAD_CSI_DATA03__SAI1_RX_BCLK 0x01F0 0x047C 0x0000 6 0 #define MX6UL_PAD_CSI_DATA03__UART5_DCE_CTS 0x01F0 0x047C 0x0000 8 0 #define MX6UL_PAD_CSI_DATA03__UART5_DTE_RTS 0x01F0 0x047C 0x0640 8 0
Adding only the one with the GPIO4_IO24 suffix (function) to your dts file will let you use the pin as GPIO.
SNVS GPIOs
Almost all of the pads declarations are shared among iMX6UL, iMX6ULL and iMX6ULZ based SoMs.
However there's is a subset of 12 PADs, providing the GPIO5 pins (the only ones available as wakeup sources) that are SoC specific:
- BOOT_MODEx (x=0,1)
- SNVS_TAMPERx (x=0,1,..,9)
For iMX6UL, these pads are declared at the beginning of arch/arm/boot/dts/imx6ul-pinfunc.h header file.
For iMX6ULL and iMX6ULZ, these pads are declared in the arch/arm/boot/dts/imx6ull-pinfunc-snvs.h header file.
In order to avoid breaking the device tree compatibility among iMX6UL, iMX6ULL and iMX6ULZ based SoMs, whenever you plan to use these GPIOs, carefully handle them within the right dtsi file.
Variscite dts files
| Device Tree Name |
SOM type |
CPU type |
Carrier Board type |
LCD Type |
Evaluation Kit name |
|---|---|---|---|---|---|
| imx6ul-var-dart.dtsi | DART-6UL | iMX6UL | VAR-6ULCustomBoard | Capacitive/ touch | VAR-STK-6UL VAR-DVK-6UL |
| imx6ull-var-dart.dtsi | DART-6UL | iMX6ULL | VAR-6ULCustomBoard | Capacitive/ touch | VAR-STK-6UL VAR-DVK-6UL |
| imx6ul-imx6ull-var-dart-common.dtsi | DART-6UL | iMX6UL/iMX6ULL | VAR-6ULCustomBoard | Capacitive/ touch | VAR-STK-6UL VAR-DVK-6UL |
For example, imx6ul-var-dart.dtsi starts with definitions and including dtsi files.
#include <dt-bindings/input/input.h> #include "imx6ul.dtsi"
The imx6ul.dtsi define the CPU platform and which pinfunc file will be included. This feature allow the pin name to be agnostic to the CPU type (i.MX6Q vs i.MX6DL)
We create 8 DTB's out of imx6ul-imx6ull-var-dart-common.dtsi.
Variscite defines dts file for each platform.
imx6ul-var-dart-nand_wifi.dts imx6ul-var-dart-sd_nand.dts imx6ul-var-dart-emmc_wifi.dts imx6ul-var-dart-sd_emmc.dts imx6ull-var-dart-nand_wifi.dts imx6ull-var-dart-sd_nand.dts imx6ull-var-dart-emmc_wifi.dts imx6ull-var-dart-sd_emmc.dts
They just define one of
/* #define WIFI */ /* #define EMMC */ /* #define NAND */
The WIFI and SCDARD share the same MMC interface. So only one of them can be activated at a time. The NAND and eMMC share the same interface I/O. So only one of them can be activated at a time.
Define a pin as GPIO in the kernel Device Tree
You need to add the relevant definitions to your device tree, as explained in the Pin Func files section above.
Edit arch/arm/boot/dts/imx6ul-var-dart.dts and add the definition for the GPIO you need in the section below.
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_hog>;
pinctrl-0 = <&pinctrl_hog_1>;
imx6ul-evk {
pinctrl_hog_1: hoggrp-1 {
fsl,pins = <
MX6UL_PAD_CSI_HSYNC__GPIO4_IO20 0x1b0b0 /* Led 1 */
MX6UL_PAD_CSI_DATA00__GPIO4_IO21 0x1b0b0 /* Led 2 */
MX6UL_PAD_GPIO1_IO00__GPIO1_IO00 0x17059 /* User Button */
MX6UL_PAD_GPIO1_IO07__ENET2_MDC 0x1b0b0
MX6UL_PAD_GPIO1_IO06__ENET2_MDIO 0x1b0b0
MX6UL_PAD_SNVS_TAMPER4__GPIO5_IO04 0x1b0b0 /* BT Enable */
>;
};
Device Tree GPIO attribute
If you look at Documentation/devicetree/bindings/pinctrl/fsl,imx6ul-pinctrl.txt in the Linux kernel source tree, the number to the right of the pin control spec can be used for additional attributes like pull-ups, pull-downs, keepers, drive strength, etc.
The value 0x80000000 is "don't know value please use the default". Else use the table below to set it to the required value.
| value |
CONFIG bits definition |
|---|---|
| (1 << 16) | PAD_CTL_HYS |
| (0 << 14) | PAD_CTL_PUS_100K_DOWN |
| (1 << 14) | PAD_CTL_PUS_47K_UP |
| (2 << 14) | PAD_CTL_PUS_100K_UP |
| (3 << 14) | PAD_CTL_PUS_22K_UP |
| (1 << 13) | PAD_CTL_PUE |
| (1 << 12) | PAD_CTL_PKE |
| (1 << 11) | PAD_CTL_ODE |
| (0 << 6) | PAD_CTL_SPEED_LOW |
| (1 << 6) | PAD_CTL_SPEED_MED |
| (2 << 6) | PAD_CTL_SPEED_MED |
| (3 << 6) | PAD_CTL_SPEED_HIGH |
| (0 << 3) | PAD_CTL_DSE_DISABLE |
| (1 << 3) | PAD_CTL_DSE_240ohm |
| (2 << 3) | PAD_CTL_DSE_120ohm |
| (3 << 3) | PAD_CTL_DSE_80ohm |
| (4 << 3) | PAD_CTL_DSE_60ohm |
| (5 << 3) | PAD_CTL_DSE_48ohm |
| (6 << 3) | PAD_CTL_DSE_40ohm |
| (7 << 3) | PAD_CTL_DSE_34ohm |
| (1 << 0) | PAD_CTL_SRE_FAST |
| (0 << 0) | PAD_CTL_SRE_SLOW |