VAR-SOM-MX7 - IEEE 1588 Hardware Timestamp

Overview of IEEE 1588 Hardware Timestamping

We recommend getting the basic overview of the IEE1588 and timestamping and basic terminologies.
Refer to https://elinux.org/images/f/f9/Introduction_to_IEEE_1588_Precision_Time_Protocol_%28PTP%29_Using_Embedded_Linux_Systems.pdf

At the very top level, it can be described as below

NXP Supports IEE1588 PTP implemented in the Ethernet SOC MAC layer.
File:IEEE Block Diagram IMX6.png

Above diagram depicts the implementation of hardware timestamping at the SOC level.
The programmable Ethernet MAC with IEEE 1588 integrates a standard IEEE 802.3. controller
Ethernet MAC with a time-stamping module, with IEEE 1588 standard provides accurate.
clock synchronization for distributed control nodes for industrial automation applications.

NXP IEE1588 PTP and timer implementation have below features:

Allows reference clock to be chosen independently of network speed.
Software-programmable precise time-stamping of ingress and egress frames.
Timer monitoring capabilities for system calibration and timing accuracy management.
Precise time-stamping of external events with programmable interrupt generation.
Programmable event and interrupt generation for external system control.
Supports hardware and software-controllable timer synchronization.
Provides a 4-channel IEEE 1588 timer. Each channel supports input capture and output compare using the 1588 counter.
Distribution of precise time information over the packet-based network.
Offers high accuracy (in the sub-microsecond range) over the network.

Hardware Setup

Network Setup: Connect the PC/Grand Master Clock Source and the target to the same Ethernet network (and use ping to verify the connection between the PC and the target).

Software

In the current setup, we will have

PC - Grand Master which acts as the clock source which has the GPS clock synchronized

Note: You may choose Device (i.MX7) as grandmaster clock as a device as well.

Device - i.MX7 with IEE1588 HW timestamp support - of which local clock to be synchronized with grandmaster

Software utilities required for PTP

$ ptp4l
$ phc2sys

For Ubuntu 16.04

$ sudo apt-get install linuxptp

Start the software base timestamping on PC or to become grandmaster clock source which you want to synchronize.

Make sure you have following device tree change present on your kernel.
Note that in this example, UART3_RX pad is disabled in order to free the pins used by the IEEE 1588 hardware timestamping for input capture.
For more about available pins and multiplexing refer to: https://www.variscite.com/wp-content/uploads/2017/12/VAR-SOM-MX7_VAR-SOM-MX7-5G_datasheet.pdf

diff --git a/arch/arm/boot/dts/imx7d-var-som.dtsi b/arch/arm/boot/dts/imx7d-var-som.dtsi
index 3f7be49..5f01fb8 100644
--- a/arch/arm/boot/dts/imx7d-var-som.dtsi
+++ b/arch/arm/boot/dts/imx7d-var-som.dtsi
@@ -573,6 +573,7 @@
                                MX7D_PAD_ENET1_RGMII_RD2__ENET1_RGMII_RD2       0x1
                                MX7D_PAD_ENET1_RGMII_RD3__ENET1_RGMII_RD3       0x1
                                MX7D_PAD_ENET1_RGMII_RX_CTL__ENET1_RGMII_RX_CTL 0x1
+                               MX7D_PAD_UART3_RX_DATA__ENET1_1588_EVENT0_IN    0x1
                        >;
                };

@@ -701,14 +702,6 @@
                        >;
                };

-               pinctrl_uart3: uart3grp {
-                       fsl,pins = <
-                               MX7D_PAD_UART3_TX_DATA__UART3_DCE_TX    0x79
-                               MX7D_PAD_UART3_RX_DATA__UART3_DCE_RX    0x79
-                               MX7D_PAD_UART3_CTS_B__UART3_DCE_CTS     0x79
-                               MX7D_PAD_UART3_RTS_B__UART3_DCE_RTS     0x79
-                       >;
-               };

                pinctrl_usdhc1_gpio: usdhc1_gpiogrp {
                        fsl,pins = <
@@ -941,11 +934,7 @@

 &uart3 {
        pinctrl-names = "default";
-       pinctrl-0 = <&pinctrl_uart3>;
-       assigned-clocks = <&clks IMX7D_UART3_ROOT_SRC>;
-       assigned-clock-parents = <&clks IMX7D_PLL_SYS_MAIN_240M_CLK>;
-       fsl,uart-has-rtscts;
-       status = "okay";
+       status = "disabled";
 };

 &usbh {

$ sudo ptp4l -i  enp5s0 -m -S

- Here, in this case, the PC sends the timestamp using software timer.
- The timestamp packets are sent over networking infrastructure via switch/router (IEEE 1588 packets)
and then once received on the target, it is used to synchronize the clock with 1μs accuracy.
- Hardware has the test and compares logic to see the drift and jitter.

Testing on device side

ptp4l works as a daemon service.
It must be started first before any system level PTP client can work.
Yocto build already contains the ptp4l required resources on the target.

root@imx7-var-som:~# ptp4l -H -A -l 7 -q -i eth0 -m -s &
ptp4l[2175.985]: config item (null).assume_two_step is 0
ptp4l[2175.985]: config item (null).check_fup_sync is 0
ptp4l[2175.985]: config item (null).tx_timestamp_timeout is 1
ptp4l[2175.985]: config item (null).clock_servo is 0
ptp4l[2175.985]: config item (null).time_stamping is 1
ptp4l[2175.985]: config item (null).clock_servo is 0
ptp4l[2175.985]: config item (null).clockClass is 248
ptp4l[2175.985]: config item (null).clockAccuracy is 254
ptp4l[2175.985]: config item (null).offsetScaledLogVariance is 65535
ptp4l[2175.985]: config item (null).productDescription is ';;'
ptp4l[2175.985]: config item (null).revisionData is ';;'
ptp4l[2175.985]: config item (null).userDescription is ''
ptp4l[2175.985]: config item (null).manufacturerIdentity is '00:00:00'
ptp4l[2175.985]: config item (null).domainNumber is 0
ptp4l[2175.986]: config item (null).slaveOnly is 1
ptp4l[2175.986]: config item (null).twoStepFlag is 1
ptp4l[2175.986]: config item (null).priority1 is 128
ptp4l[2175.986]: config item (null).priority2 is 128
ptp4l[2175.986]: config item (null).gmCapable is 1
ptp4l[2175.986]: config item (null).gmCapable is 1
ptp4l[2175.986]: config item (null).free_running is 0
ptp4l[2175.986]: selected /dev/ptp0 as PTP clock
ptp4l[2175.986]: config item (null).uds_address is '/var/run/ptp4l'
ptp4l[2175.986]: section item /var/run/ptp4l.announceReceiptTimeout now 0
ptp4l[2175.986]: section item /var/run/ptp4l.delay_mechanism now 0
ptp4l[2175.986]: section item /var/run/ptp4l.network_transport now 0
ptp4l[2175.986]: section item /var/run/ptp4l.delay_filter_length now 1
ptp4l[2175.986]: config item (null).free_running is 0
ptp4l[2175.986]: config item (null).freq_est_interval is 1
ptp4l[2175.986]: config item (null).gmCapable is 1
ptp4l[2175.986]: config item (null).kernel_leap is 1
ptp4l[2175.986]: config item (null).timeSource is 160
ptp4l[2175.986]: config item (null).pi_proportional_const is 0.000000
ptp4l[2175.986]: config item (null).pi_integral_const is 0.000000
ptp4l[2175.986]: config item (null).pi_proportional_scale is 0.000000
ptp4l[2175.986]: config item (null).pi_proportional_exponent is -0.300000
ptp4l[2175.986]: config item (null).pi_proportional_norm_max is 0.700000
ptp4l[2175.986]: config item (null).pi_integral_scale is 0.000000
ptp4l[2175.986]: config item (null).pi_integral_exponent is 0.400000
ptp4l[2175.986]: config item (null).pi_integral_norm_max is 0.300000
ptp4l[2175.986]: config item (null).step_threshold is 0.000000
ptp4l[2175.986]: config item (null).first_step_threshold is 0.000020
ptp4l[2175.986]: config item (null).max_frequency is 900000000
ptp4l[2175.986]: config item (null).tsproc_mode is 0
ptp4l[2175.986]: config item (null).delay_filter is 1
ptp4l[2175.986]: config item (null).delay_filter_length is 10
ptp4l[2175.986]: config item (null).summary_interval is 0
ptp4l[2175.986]: config item (null).sanity_freq_limit is 200000000
ptp4l[2175.986]: PI servo: sync interval 1.000 kp 0.700 ki 0.300000
ptp4l[2175.987]: config item /var/run/ptp4l.boundary_clock_jbod is 0
ptp4l[2175.987]: config item /var/run/ptp4l.network_transport is 0
ptp4l[2175.987]: config item /var/run/ptp4l.delayAsymmetry is 0
ptp4l[2175.987]: config item /var/run/ptp4l.follow_up_info is 0
ptp4l[2175.987]: config item /var/run/ptp4l.freq_est_interval is 1
ptp4l[2175.987]: config item /var/run/ptp4l.hybrid_e2e is 0
ptp4l[2175.987]: config item /var/run/ptp4l.path_trace_enabled is 0
ptp4l[2175.987]: config item /var/run/ptp4l.ingressLatency is 0
ptp4l[2175.987]: config item /var/run/ptp4l.egressLatency is 0
ptp4l[2175.987]: config item /var/run/ptp4l.delay_mechanism is 0
ptp4l[2175.987]: config item /var/run/ptp4l.fault_badpeernet_interval is 16
ptp4l[2175.987]: config item /var/run/ptp4l.fault_reset_interval is 4
ptp4l[2175.987]: config item /var/run/ptp4l.tsproc_mode is 0
ptp4l[2175.987]: config item /var/run/ptp4l.delay_filter is 1
ptp4l[2175.987]: config item /var/run/ptp4l.delay_filter_length is 1
ptp4l[2175.987]: config item eth0.boundary_clock_jbod is 0
ptp4l[2175.987]: config item eth0.network_transport is 1
ptp4l[2176.285]: config item eth0.delayAsymmetry is 0
ptp4l[2176.285]: config item eth0.follow_up_info is 0
ptp4l[2176.285]: config item eth0.freq_est_interval is 1
ptp4l[2176.285]: config item eth0.hybrid_e2e is 0
ptp4l[2176.285]: config item eth0.path_trace_enabled is 0
ptp4l[2176.285]: config item eth0.ingressLatency is 0
ptp4l[2176.285]: config item eth0.egressLatency is 0
ptp4l[2176.285]: config item eth0.delay_mechanism is 0
ptp4l[2176.285]: config item eth0.fault_badpeernet_interval is 16
ptp4l[2176.285]: config item eth0.fault_reset_interval is 4
ptp4l[2176.285]: config item eth0.tsproc_mode is 0
ptp4l[2176.286]: config item eth0.delay_filter is 1
ptp4l[2176.286]: config item eth0.delay_filter_length is 10
ptp4l[2176.286]: config item eth0.logMinDelayReqInterval is 0
ptp4l[2176.286]: config item eth0.logAnnounceInterval is 1
ptp4l[2176.286]: config item eth0.announceReceiptTimeout is 3
ptp4l[2176.286]: config item eth0.syncReceiptTimeout is 0
ptp4l[2176.286]: config item eth0.transportSpecific is 0
ptp4l[2176.286]: config item eth0.logSyncInterval is 0
ptp4l[2176.286]: config item eth0.logMinPdelayReqInterval is 0
ptp4l[2176.286]: config item eth0.neighborPropDelayThresh is 20000000
ptp4l[2176.286]: config item eth0.min_neighbor_prop_delay is -20000000
ptp4l[2176.286]: config item eth0.udp_ttl is 1
ptp4l[2176.287]: driver changed our HWTSTAMP options
ptp4l[2176.287]: tx_type   1 not 1
ptp4l[2176.287]: rx_filter 1 not 12
ptp4l[2176.287]: config item (null).dscp_event is 0
ptp4l[2176.287]: config item (null).dscp_general is 0
ptp4l[2176.287]: port 1: INITIALIZING to LISTENING on INITIALIZE
ptp4l[2176.287]: config item /var/run/ptp4l.logMinDelayReqInterval is 0
ptp4l[2176.287]: config item /var/run/ptp4l.logAnnounceInterval is 1
ptp4l[2176.287]: config item /var/run/ptp4l.announceReceiptTimeout is 0
ptp4l[2176.287]: config item /var/run/ptp4l.syncReceiptTimeout is 0
ptp4l[2176.287]: config item /var/run/ptp4l.transportSpecific is 0
ptp4l[2176.287]: config item /var/run/ptp4l.logSyncInterval is 0
ptp4l[2176.287]: config item /var/run/ptp4l.logMinPdelayReqInterval is 0
ptp4l[2176.287]: config item /var/run/ptp4l.neighborPropDelayThresh is 20000000
ptp4l[2176.287]: config item /var/run/ptp4l.min_neighbor_prop_delay is -20000000
ptp4l[2176.287]: config item (null).uds_address is '/var/run/ptp4l'
ptp4l[2176.287]: port 0: INITIALIZING to LISTENING on INITIALIZE
ptp4l[2176.288]: interface index 1 is up
ptp4l[2176.288]: interface index 2 is down
ptp4l[2176.288]: interface index 3 is up
ptp4l[2176.288]: port 1: link up
ptp4l[2176.288]: interface index 4 is down
ptp4l[2176.288]: interface index 5 is down
ptp4l[2176.288]: interface index 6 is down

Testing on device side - (Local clock Synchronization)

The previous step allows the device to receive and make the HW time stamp available to the
Local clock source or application. phyc2sys utility works in conjunction with the ptp4l utility to synchronize the
local system clock with the grand master clock.

root@imx7-var-som:~# phc2sys -s /dev/ptp0 -w -l 6 -q -m 
phc2sys[561.207]: Waiting for ptp4l...
phc2sys[562.208]: phc offset 1464418821463523 s0 freq      +0 delay   3000
phc2sys[563.208]: phc offset 1464419821714028 s1 freq +100000000 delay   2667
phc2sys[586.213]: phc offset 23005021015 s2 freq +100000000 delay   2400
phc2sys[587.214]: phc offset 24005243215 s2 freq +100000000 delay   2400
phc2sys[588.214]: phc offset 25005490315 s2 freq +100000000 delay   2400
phc2sys[589.214]: phc offset 26005730816 s2 freq +100000000 delay   2400
phc2sys[590.214]: phc offset 27005974016 s2 freq +100000000 delay   2400
phc2sys[591.214]: phc offset 28006201017 s2 freq +100000000 delay   2400
phc2sys[592.215]: phc offset 29006428317 s2 freq +100000000 delay   2400
phc2sys[593.215]: phc offset 30006676017 s2 freq +100000000 delay   2400
phc2sys[594.215]: phc offset 31006943218 s2 freq +100000000 delay   2400
phc2sys[595.215]: phc offset 32007195118 s2 freq +100000000 delay   2400
phc2sys[596.216]: phc offset 33007442819 s2 freq +100000000 delay   2400
phc2sys[597.216]: phc offset 34007662169 s2 freq +100000000 delay   2700
phc2sys[598.216]: phc offset 35007934919 s2 freq +100000000 delay   2400
phc2sys[599.216]: phc offset 36008207820 s2 freq +100000000 delay   2400
phc2sys[600.217]: phc offset 37008466620 s2 freq +100000000 delay   2400
phc2sys[601.217]: phc offset 38008680421 s2 freq +100000000 delay   2400
phc2sys[602.217]: phc offset 39008935621 s2 freq +100000000 delay   2400
phc2sys[603.217]: phc offset 40009183021 s2 freq +100000000 delay   2400
phc2sys[604.218]: phc offset 41009422622 s2 freq +100000000 delay   2400
phc2sys[605.218]: phc offset 42009670922 s2 freq +100000000 delay   2400
phc2sys[606.218]: phc offset 43009915323 s2 freq +100000000 delay   2400
phc2sys[607.218]: phc offset 44010150723 s2 freq +100000000 delay   2400
phc2sys[608.219]: phc offset 45010369773 s2 freq +100000000 delay   2700
phc2sys[609.219]: phc offset 46010583124 s2 freq +100000000 delay   2400
phc2sys[610.219]: phc offset 47010823024 s2 freq +100000000 delay   2400
phc2sys[611.219]: phc offset 48010995125 s2 freq +100000000 delay   2400
phc2sys[612.219]: phc offset 49011205925 s2 freq +100000000 delay   2400
phc2sys[613.220]: phc offset 50011483625 s2 freq +100000000 delay   2400
phc2sys[614.220]: phc offset 51011699826 s2 freq +100000000 delay   2400
phc2sys[615.220]: phc offset 52011934926 s2 freq +100000000 delay   2400
phc2sys[616.220]: phc offset 53012195227 s2 freq +100000000 delay   2400
phc2sys[617.221]: phc offset 54012428677 s2 freq +100000000 delay   2700
phc2sys[618.221]: phc offset 55012704577 s2 freq +100000000 delay   2700
root@imx7-var-som:~#

HW Events

After kernel up, run commands:

$ ptp4l -A -4 -H -m -i eth0  &

$ echo 1 > /sys/class/ptp/ptp0/pps_enable

VAR-SOM-MX7 Eth IEEE.1588

Contents