VAR-SOM-MX6 UART
Test
By default, Variscite configured UART3 (ttymxc2).
To test it:
Use minicom to connect.
Set the serial to /dev/ttymxc2
You can use a loopback or connect to anther computer
Example: configure UART4, ttymxc3
Note: The pins here are set arbitrarily. You should set them based on your hardware design, and make sure they are not conflicting with other devices in the device tree.
After applying tthe changes below, continue following the "Build Linux from source code" guide to build only the device trees and to copy them to your SD card.
VAR-SOM-SOLO / VAR-SOM-DUAL / VAR-SOM-MX6
Edit arch/arm/boot/dts/imx6qdl-var-som.dtsi Look for:
/* ttymxc2 UART */ &uart3 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart3_2>; fsl,uart-has-rtscts; status = "okay"; };
Duplicate it and change the name and the pinctrl name. For Example:
&uart4 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart4_1>; fsl,uart-has-rtscts; status = "okay"; };
Duplicate the corresponding pinctrl. Copy :
/* Variscite Uart3 support */ pinctrl_uart3_2: uart3grp-2 { /* RX/TX RTS/CTS */ fsl,pins = < MX6QDL_PAD_EIM_D25__UART3_RX_DATA 0x1b0b1 MX6QDL_PAD_EIM_D24__UART3_TX_DATA 0x1b0b1 MX6QDL_PAD_EIM_D23__UART3_CTS_B 0x1b0b1 MX6QDL_PAD_EIM_EB3__UART3_RTS_B 0x1b0b1 >; };
Into:
/* Variscite Uart4 support */ pinctrl_uart4_1: uart4grp-1 { /* RX/TX RTS/CTS */ fsl,pins = < MX6QDL_PAD_KEY_ROW0__UART4_RX_DATA 0x1b0b1 MX6QDL_PAD_KEY_COL0__UART4_TX_DATA 0x1b0b1 MX6QDL_PAD_CSI0_DAT16__UART4_RTS_B 0x1b0b1 MX6QDL_PAD_CSI0_DAT17__UART4_CTS_B 0x1b0b1 >; };
DART-MX6
Edit arch/arm/boot/dts/imx6qdl-var-dart.dtsi Look for:
/* ttymxc2 UART */ &uart3 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart3_2>; fsl,uart-has-rtscts; status = "okay"; };
Duplicate it and change the name and the pinctrl name. For Example:
&uart4 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart4_1>; status = "okay"; };
Duplicate the corresponding pinctrl. Copy :
/* Variscite Uart3 support */ pinctrl_uart3_2: uart3grp-2 { /* RX/TX RTS/CTS */ fsl,pins = < MX6QDL_PAD_EIM_D25__UART3_RX_DATA 0x1b0b1 MX6QDL_PAD_EIM_D24__UART3_TX_DATA 0x1b0b1 MX6QDL_PAD_EIM_D23__UART3_CTS_B 0x1b0b1 MX6QDL_PAD_EIM_EB3__UART3_RTS_B 0x1b0b1 >; };
Into:
/* Variscite Uart4 support */ pinctrl_uart4_1: uart4grp-1 { /* RX/TX */ fsl,pins = < MX6QDL_PAD_KEY_ROW0__UART4_RX_DATA 0x1b0b1 MX6QDL_PAD_KEY_COL0__UART4_TX_DATA 0x1b0b1 >; };