DART-6UL SPI

DART-6UL/VAR-SOM-MX7 - SPI

In this example we will show how to configure SPI 1 and SPI 2 to work on SOM

Kernel configuration

Verify that the User mode SPI driver (CONFIG_SPI_SPIDEV) is enabled in your kernel configuration:

• In menuconfig: Device Drivers -> SPI support -> <*> User mode SPI device driver support
  

SPI 1 on 6UL Custom Board and Condcerto Board

Add spidev to your device tree

&ecspi1 {
	fsl,spi-num-chipselects = <1>;
	cs-gpios = <&gpio4 26 0>;
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_ecspi1_1>;
	status = "okay";

        chip1: spidev@0 {
               compatible = "spidev";
               spi-max-frequency = <12000000>;
               reg = <0>;
        };
};

Add pin control to your device tree

&iomuxc {
	pinctrl_ecspi1_1: ecspi1grp {
		fsl,pins = <
			MX6UL_PAD_CSI_DATA07__ECSPI1_MISO       0x100b1
			MX6UL_PAD_CSI_DATA06__ECSPI1_MOSI       0x100b1
			MX6UL_PAD_CSI_DATA04__ECSPI1_SCLK       0x100b1
			MX6UL_PAD_CSI_DATA05__GPIO4_IO26        0x100b1
		>;
	};

};

Note: The pins here were set arbitrarily. You should set them based on your hardware design, and make sure they are not conflicting with other devices in the device tree.
you can also have multiple chip selects.

SPI 2 on 6UL Custom Board

Add spidev to your device tree

&ecspi2 {
	fsl,spi-num-chipselects = <1>;
	cs-gpios = <&gpio4 22 0>;
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_ecspi2_1>;
	status = "okay";

	spidev@0 {
               compatible = "spidev";
               spi-max-frequency = <12000000>;
               reg = <0>;
        };
};

Add pin control to your device tree

&iomuxc {
	pinctrl_ecspi2_1: ecspi2grp {
		fsl,pins = <
			MX6UL_PAD_CSI_DATA03__ECSPI2_MISO	0x100b1
			MX6UL_PAD_CSI_DATA02__ECSPI2_MOSI	0x100b1
			MX6UL_PAD_CSI_DATA00__ECSPI2_SCLK	0x100b1
			MX6UL_PAD_CSI_DATA01__GPIO4_IO22	0x100b1
		>;
	};
};

Note: The pins here were set arbitrarily. You should set them based on your hardware design, and make sure they are not conflicting with other devices in the device tree.
you can also have multiple chip selects.

SPI 2 on Concerto Board

Add spidev to your device tree

&ecspi2 {
	fsl,spi-num-chipselects = <1>;
	cs-gpios = <&gpio1 29 0>;
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_ecspi2_1>;
	status = "okay";

	spidev@0 {
               compatible = "spidev";
               spi-max-frequency = <12000000>;
               reg = <0>;
        };
};

Add pin control to your device tree

&iomuxc {
	pinctrl_ecspi2_1: ecspi2grp {
		fsl,pins = <
			MX6UL_PAD_UART5_TX_DATA__ECSPI2_MOSI	0x100b1
			MX6UL_PAD_UART5_RX_DATA__ECSPI2_MISO	0x100b1
			MX6UL_PAD_UART4_TX_DATA__ECSPI2_SCLK	0x100b1
			MX6UL_PAD_UART4_RX_DATA__GPIO1_IO29	0x100b1
		>;
	};
};

Note: The pins here were set arbitrarily. You should set them based on your hardware design, and make sure they are not conflicting with other devices in the device tree.
you can also have multiple chip selects.

Compile

Compile the kernel and device tree and update the SOM.

Testing

There's an SPI testing utility C code example in the kernel source tree: tools/spi/spidev_test.c (in older kernels: Documentation/spi/spidev_test.c)
To cross compile it use the following command:

$ $CC ./tools/spi/spidev_test.c -o ./spidev_test

SPI 1

SPI 1 will be accessible on the following EVK pins:

• J11.2 - SPI1.CLK
• J11.6 - SPI1.MISO
• J11.8 - SPI1.MOSI
• J11.4 - SPI1.SS0

SPI 2

SPI 2 will be accessible on the following EVK pins:

• J11.9 - SPI2.CLK
• J13.2 - SPI2.MISO
• J6.7 - SPI2.MOSI
• J6.5 - SPI2.SS0