VAR-SOM-MX6 Camera FSLC

VAR-SOM-MX6 - Camera

Testing our mipi cameras

$ export DISPLAY=:0

$ gst-launch-1.0 imxv4l2videosrc device=/dev/video0 ! imxeglvivsink

You can find more examples in the GStreamer section.

Adding a parallel camera

To add a parallel camera support to the kernel:
As usual, make sure the driver for your device (camera) is included in the kernel configuration (use menuconfig), and define in the device tree the pins and driver to be used.
The device tree for VAR-SOM-MX6 is arch/arm/boot/dts/imx6qdl-var-som.dtsi
The device tree for DART-MX6 is arch/arm/boot/dts/imx6qdl-var-dart.dtsi
For example:

&iomuxc {
        pinctrl-names = "default";
        pinctrl-0 = <&pinctrl_hog>;

        imx6qdl-var-som-mx6 {

                pinctrl_hog: hoggrp {
                        fsl,pins = <
				...

                                /* Camera Clock */
                                MX6QDL_PAD_GPIO_3__CCM_CLKO2            0x130b0
                        >;
                };

		...

                pinctrl_ipu1_2: ipu1grp-2 { /* parallel camera */
                        fsl,pins = <
                                MX6QDL_PAD_CSI0_DAT12__IPU1_CSI0_DATA12         0x80000000
                                MX6QDL_PAD_CSI0_DAT13__IPU1_CSI0_DATA13         0x80000000
                                MX6QDL_PAD_CSI0_DAT14__IPU1_CSI0_DATA14         0x80000000
                                MX6QDL_PAD_CSI0_DAT15__IPU1_CSI0_DATA15         0x80000000
                                MX6QDL_PAD_CSI0_DAT16__IPU1_CSI0_DATA16         0x80000000
                                MX6QDL_PAD_CSI0_DAT17__IPU1_CSI0_DATA17         0x80000000
                                MX6QDL_PAD_CSI0_DAT18__IPU1_CSI0_DATA18         0x80000000
                                MX6QDL_PAD_CSI0_DAT19__IPU1_CSI0_DATA19         0x80000000
                                MX6QDL_PAD_CSI0_DATA_EN__IPU1_CSI0_DATA_EN      0x80000000
                                MX6QDL_PAD_CSI0_PIXCLK__IPU1_CSI0_PIXCLK        0x80000000
                                MX6QDL_PAD_CSI0_MCLK__IPU1_CSI0_HSYNC           0x80000000
                                MX6QDL_PAD_CSI0_VSYNC__IPU1_CSI0_VSYNC          0x80000000
                                MX6QDL_PAD_SD1_DAT1__GPIO1_IO17                 0x80000000
                                MX6QDL_PAD_SD1_DAT0__GPIO1_IO16                 0x80000000
                        >;
                };

		...
	};
};

...

i2c1 {
        clock-frequency = <100000>;
        pinctrl-names = "default";
        pinctrl-0 = <&pinctrl_i2c1>;
        status = "okay";

        ov564x: ov564x@3c {
                compatible = "ovti,ov564x";
                reg = <0x3c>;
                pinctrl-names = "default";
                pinctrl-0 = <&pinctrl_ipu1_2>;
                clocks = <&clks 200>;
                clock-names = "csi_mclk";
                pwn-gpios = <&gpio1 16 1>;   /* active low: SD1_DAT0 */
                rst-gpios = <&gpio1 17 0>;   /* active high: SD1_DAT1 */
                csi_id = <0>;
                mclk = <24000000>;
                mclk_source = <0>;
        };
};

Note: This is just an example. You should set everything according to your camera model and hardware design, and make sure the pins are not conflicting with other devices in the device tree.


In addition, you need to patch arch/arm/mach-imx/mach-imx6q.c to set the appropriate GPR bits for connecting the desired CSI to the parallel interface.
For example:

diff --git a/arch/arm/mach-imx/mach-imx6q.c b/arch/arm/mach-imx/mach-imx6q.c
index ae5c3cd..99cac45 100644
--- a/arch/arm/mach-imx/mach-imx6q.c
+++ b/arch/arm/mach-imx/mach-imx6q.c
@@ -232,11 +232,11 @@ put_node:
 static void __init imx6q_csi_mux_init(void)
 {
        /*
-        * MX6Q SabreSD board:
+        * MX6Q SabreSD/VAR-SOM-MX6 boards:
         * IPU1 CSI0 connects to parallel interface.
         * Set GPR1 bit 19 to 0x1.
         *
-        * MX6DL SabreSD board:
+        * MX6DL SabreSD/VAR-SOM-MX6 boards:
         * IPU1 CSI0 connects to parallel interface.
         * Set GPR13 bit 0-2 to 0x4.
         * IPU1 CSI1 connects to MIPI CSI2 virtual channel 1.
@@ -247,10 +247,12 @@ static void __init imx6q_csi_mux_init(void)
        gpr = syscon_regmap_lookup_by_compatible("fsl,imx6q-iomuxc-gpr");
        if (!IS_ERR(gpr)) {
                if (of_machine_is_compatible("fsl,imx6q-sabresd") ||
-                       of_machine_is_compatible("fsl,imx6q-sabreauto"))
+                       of_machine_is_compatible("fsl,imx6q-sabreauto") ||
+                       of_machine_is_compatible("fsl,imx6q-var-som"))
                        regmap_update_bits(gpr, IOMUXC_GPR1, 1 << 19, 1 << 19);
                else if (of_machine_is_compatible("fsl,imx6dl-sabresd") ||
-                        of_machine_is_compatible("fsl,imx6dl-sabreauto"))
+                        of_machine_is_compatible("fsl,imx6dl-sabreauto") ||
+                        of_machine_is_compatible("fsl,imx6dl-var-som"))
                        regmap_update_bits(gpr, IOMUXC_GPR13, 0x3F, 0x0C);
        } else {
                pr_err("%s(): failed to find fsl,imx6q-iomux-gpr regmap\n",