VAR-SOM-MX7 GPIO

VAR-SOM-MX7 - GPIO

GPIO state

The current state of the system's GPIOs can be obtained in user-mode, as shown in the following example:

root@imx7-var-som:~# cat /sys/kernel/debug/gpio
GPIOs 0-31, platform/30200000.gpio, 30200000.gpio:
 gpio-4   (wlreg_on            ) out lo    
 gpio-5   (usb_otg1_vbus       ) out lo    
 gpio-7   (usb_otg2_vbus       ) out lo    
 gpio-9   (ads7846_pendown     ) in  hi    
 gpio-10  (hsic_hub_pwr_on     ) out lo    
 gpio-11  (Back                ) in  hi    
 gpio-12  (reg_hsic_hub_connect) out lo    
 gpio-14  (sysfs               ) out lo    

GPIOs 32-63, platform/30210000.gpio, 30210000.gpio:
 gpio-46  (can2-3v3            ) out lo    
 gpio-60  (Menu                ) in  hi    
 gpio-61  (Home                ) in  hi    

GPIOs 64-95, platform/30220000.gpio, 30220000.gpio:

GPIOs 96-127, platform/30230000.gpio, 30230000.gpio:
 gpio-99  (phy-reset           ) out lo    
 gpio-115 (spi_imx             ) out lo    
 gpio-119 (spi_imx             ) out lo    

GPIOs 128-159, platform/30240000.gpio, 30240000.gpio:
 gpio-128 (cd                  ) in  lo    
 gpio-130 (VDD_SD1             ) out lo    

GPIOs 160-191, platform/30250000.gpio, 30250000.gpio:

GPIOs 192-223, platform/30260000.gpio, 30260000.gpio:

Each GPIO is defined as in or out and the state is shown as lo or hi.
For example pin 128 is the SD card card-detect. When an SD card is plugged in, the state will be:

 gpio-128 (cd                  ) in  lo

When the SD card is removed, the state will be:

 gpio-128 (cd                  ) in  hi

Manipulating a single GPIO via /sys/class/gpio

Using a command line or a script

GPIOs in i.MX are grouped in groups of 32 pins.
For example, GPIO1_3 belong to the first group, pin 3. Its absolute number will be 3.
GPIO7_4 will be (7-1)*32+4=196.
Assuming this GPIO is defined in your device tree, the following is an example of how to use it from userspace.

To configure as output:

$ echo 196 > /sys/class/gpio/export
$ echo out > /sys/class/gpio/gpio196/direction

Set GPIO high:

$ echo 1 > /sys/class/gpio/gpio196/value

Set GPIO low:

$ echo 0 > /sys/class/gpio/gpio196/value

To configure as input:

$ echo 196 > /sys/class/gpio/export
$ echo in > /sys/class/gpio/gpio196/direction

Read the current value:

$ cat /sys/class/gpio/gpio196/value

To free the GPIO after you're done using it:

$echo 196 > /sys/class/gpio/unexport

Using a C application

All of the command line operations above can be translated to C code:
Reserve (export) the GPIO:

#define IMX_GPIO_NR(port, index)    ((((port)-1)*32)+((index)&31))

int fd;
char buf[MAX_BUF]; 
int gpio = IMX_GPIO_NR(7, 4); /* Just an example */

fd = open("/sys/class/gpio/export", O_WRONLY);

sprintf(buf, "%d", gpio); 

write(fd, buf, strlen(buf));

close(fd);

Set the GPIO direction:

sprintf(buf, "/sys/class/gpio/gpio%d/direction", gpio);

fd = open(buf, O_WRONLY);

/* Set out direction */
write(fd, "out", 3); 
/* Set in direction */
write(fd, "in", 2); 

close(fd);

In case of out direction set the GPIO value:

sprintf(buf, "/sys/class/gpio/gpio%d/value", gpio);

fd = open(buf, O_WRONLY);

/* Set GPIO high status */
write(fd, "1", 1); 
/* Set GPIO low status */
write(fd, "0", 1); 

close(fd);

In case of in direction get the current GPIO value:

char value;

sprintf(buf, "/sys/class/gpio/gpio%d/value", gpio);

fd = open(buf, O_RDONLY);

read(fd, &value, 1);

if (value == '0') { 
     /* Current GPIO status low */
} else {
     /* Current GPIO status high */
}

close(fd);

Once finished, free (unexport) the GPIO:

fd = open("/sys/class/gpio/unexport", O_WRONLY);

sprintf(buf, "%d", gpio);

write(fd, buf, strlen(buf));

close(fd);

Important notes:

• Remember that after the first read operation the file pointer will move to the next position in the file, so to get a correct value for each read operation you simply have to set the file pointer at the beginning of the file before read by using the following command:

lseek(fd, 0, SEEK_SET);

• This is only a short example. If you want to use it in your code remember add error handling to it.

Kernel Device Tree GPIO configuration

Device Tree GPIO files

Pin Func files

In the directory arch/arm/boot/dts/ of the Linux kernel source you will find the pin functions definitions files.
The relevant files are imx7d-pinfunc-lpsr.h (the first 8 GPIOs), and imx7d-pinfunc.h (the rest).
If you edit it and search for GPIO4_IO13, for example, you will see a group of definitions with same prefix (pad name), "MX7D_PAD_I2C3_SDA".

#define MX7D_PAD_I2C3_SDA__I2C3_SDA                               0x015C 0x03CC 0x05E8 0x0 0x2
#define MX7D_PAD_I2C3_SDA__UART5_DCE_RTS                          0x015C 0x03CC 0x0710 0x1 0x1
#define MX7D_PAD_I2C3_SDA__UART5_DTE_CTS                          0x015C 0x03CC 0x0000 0x1 0x0
#define MX7D_PAD_I2C3_SDA__FLEXCAN2_TX                            0x015C 0x03CC 0x0000 0x2 0x0
#define MX7D_PAD_I2C3_SDA__CSI_HSYNC                              0x015C 0x03CC 0x0518 0x3 0x1
#define MX7D_PAD_I2C3_SDA__SDMA_EXT_EVENT1                        0x015C 0x03CC 0x06DC 0x4 0x1
#define MX7D_PAD_I2C3_SDA__GPIO4_IO13                             0x015C 0x03CC 0x0000 0x5 0x0
#define MX7D_PAD_I2C3_SDA__EPDC_BDR1                              0x015C 0x03CC 0x0000 0x6 0x0

Adding only the one with the GPIO4_IO13 suffix (function) to your dts file will let you use the pin as GPIO.

Variscite dts files

There are two dts files for the VAR-SOM-MX7, one for SOMs with eMMC, and one for SOMs with NAND flash:

imx7d-var-som-emmc.dts
imx7d-var-som-nand.dts

Each of them includes our common arch/arm/boot/dts/imx7d-var-som.dtsi and adds the definitions of the relevant storage (eMMC/NAND flash).
At the top of imx7d-var-som.dtsi there are the following includes:

#include <dt-bindings/input/input.h>
#include "imx7d.dtsi"

The imx7d.dtsi defines the CPU platform and includes the appropriate pinfunc header files.

Define a pin as GPIO in the kernel Device Tree

You need to add the relevant definitions to your device tree, as explained in the Pin Func files section above.
Edit arch/arm/boot/dts/imx7d-var-som.dtsi and add the definition for the GPIO you need in one of the sections below.

For the first 8 GPIOs:

&iomuxc_lpsr {
        pinctrl-names = "default";
        pinctrl-0 = <&pinctrl_hog_2 &pinctrl_usbotg2_pwr_2>;

        imx7d-sdb {
                pinctrl_hog_2: hoggrp-2 {
                        fsl,pins = <
                                MX7D_PAD_GPIO1_IO05__GPIO1_IO5          0x14
                        >;
                };

For the rest:

&iomuxc {
        pinctrl-names = "default";
        pinctrl-0 = <&pinctrl_hog_1>;

        imx7d-sdb {
                pinctrl_hog_1: hoggrp-1 {
                        fsl,pins = <
                                MX7D_PAD_GPIO1_IO14__GPIO1_IO14         0x80000000  /* bt reg on */
                                MX7D_PAD_EPDC_PWR_COM__GPIO2_IO30       0x80000000  /* capacitive touch irq */
                                MX7D_PAD_SD2_RESET_B__GPIO5_IO11        0x59  /* ethphy0 reset */
                                MX7D_PAD_UART2_TX_DATA__GPIO4_IO3       0x59  /* ethphy1 reset */
                                MX7D_PAD_GPIO1_IO10__GPIO1_IO10         0x59  /* hsic hub reset */
                                MX7D_PAD_GPIO1_IO12__GPIO1_IO12         0x59  /* hsic hub connect */
                                MX7D_PAD_GPIO1_IO13__GPIO1_IO13         0x59  /* LED */
                                MX7D_PAD_SD1_WP__CCM_CLKO2              0xb0  /* camera clock */
                        >;
                };

Device Tree GPIO attribute

If you look at Documentation/devicetree/bindings/pinctrl/fsl,imx7d-pinctrl.txt in the Linux kernel source tree, the number to the right of the pin control spec can be used for additional attributes like pull-ups, pull-downs, keepers, drive strength, etc.
The value 0x80000000 is "don't know value please use the default". Else use the table below to set it to the required value.

CONFIG bits definition	value
PAD_CTL_PUS_100K_DOWN	(0 << 5)
PAD_CTL_PUS_5K_UP	(1 << 5)
PAD_CTL_PUS_47K_UP	(2 << 5)
PAD_CTL_PUS_100K_UP	(3 << 5)
PAD_CTL_PUE	(1 << 4)
PAD_CTL_HYS	(1 << 3)
PAD_CTL_SRE_SLOW	(1 << 2)
PAD_CTL_SRE_FAST	(0 << 2)
PAD_CTL_DSE_X1	(0 << 0)
PAD_CTL_DSE_X2	(1 << 0)
PAD_CTL_DSE_X3	(2 << 0)
PAD_CTL_DSE_X4	(3 << 0)