Template:M4 LINUX DEMO: Difference between revisions
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(Make AN5317 show on MX8M machines) |
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The Linux remoteproc framework can be used to load the Cortex {{#var:CORTEX_M_TYPE}} firmware from Linux userspace. | The Linux remoteproc framework can be used to load the Cortex {{#var:CORTEX_M_TYPE}} firmware from Linux userspace. | ||
{{#switch: {{#var:HARDWARE_NAME}} | {{#switch: {{#var:HARDWARE_NAME}} | ||
| DART-MX8M-PLUS = | | DART-MX8M-PLUS | ||
| VAR-SOM-MX8M-NANO | |||
| DART-MX8M-MINI | |||
| DART-MX8M = | |||
{{Note|'''Note:''' As of 7 October 2024, [https://www.nxp.com/docs/en/application-note/AN5317.pdf NXP Application Note AN5317] states the following:<br><br> | {{Note|'''Note:''' As of 7 October 2024, [https://www.nxp.com/docs/en/application-note/AN5317.pdf NXP Application Note AN5317] states the following:<br><br> | ||
On i.MX 8M platforms, "remoteproc" stops only the Cortex-M CPU, not the Cortex-M system. Therefore, any in-flight Cortex-M bus transactions would hang after the CPU is halted and this can only be resolved with a full SoC reset. It is not recommended to stop the Cortex-M7 CPU in a production system. If the system must stop the Cortex-M7 CPU, reload the image and restart it. Then, the Cortex-M7 CPU must be in the WFI state and have no external access to the Cortex-M7 TCM memory through eDMA or other similar transactions. A possible solution is to implement a handshake between the Cortex-M and Cortex-A CPUs to confirm that the Cortex-M CPU is safe to stop or reset.}} | On i.MX 8M platforms, "remoteproc" stops only the Cortex-M CPU, not the Cortex-M system. Therefore, any in-flight Cortex-M bus transactions would hang after the CPU is halted and this can only be resolved with a full SoC reset. It is not recommended to stop the Cortex-M7 CPU in a production system. If the system must stop the Cortex-M7 CPU, reload the image and restart it. Then, the Cortex-M7 CPU must be in the WFI state and have no external access to the Cortex-M7 TCM memory through eDMA or other similar transactions. A possible solution is to implement a handshake between the Cortex-M and Cortex-A CPUs to confirm that the Cortex-M CPU is safe to stop or reset.}} | ||