VAR-SOM-AM62 rev changelog: Difference between revisions
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| Yocto Dunfell (kernel 5.10.168) | | Yocto Dunfell (kernel 5.10.168) | ||
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<li>[https://github.com/varigit | <li>[https://github.com/varigit/ti-u-boot/commit/06317a660fb7602acea5d7780deaf84154765490 Revert "am65-cpsw-nuss: fix inverted rgmii_id bit"]</li> | ||
<li>[https://github.com/varigit | <li>[https://github.com/varigit/ti-u-boot/commit/c9ccad284ab88c0fee4613e0d286319c0a6c173e net: ti: am65-cpsw-nuss: Remove incorrect RGMII_ID bit functionality]</li> | ||
<li>[https://github.com/varigit | <li>[https://github.com/varigit/ti-u-boot/commit/ba9673d0e8533fe902749e08ff965e9cd27b1e06 net: ti: am65-cpsw-nuss: Support Variscite RGMII_ID board quirk]</li> | ||
<li>[https://github.com/varigit | <li>[https://github.com/varigit/ti-u-boot/commit/5f2aa36dfe9013e02b71ec49a7ab14dfef30441e variscite: am62x_eeprom: Use BIT macros for bits]</li> | ||
<li>[https://github.com/varigit | <li>[https://github.com/varigit/ti-u-boot/commit/5d46e4b15451298866c151d6fadfe3b01068b3b4 variscite: am62x_eeprom: Add feature bit for RGMII_ID assembly quirk]</li> | ||
<li>[https://github.com/varigit | <li>[https://github.com/varigit/ti-u-boot/commit/be7fff0e0a0305361e10b9453ce244c57e3ba294 variscite: am62x_eth: Add function to check RGMII_ID quirk from eeprom]</li> | ||
<li>[https://github.com/varigit | <li>[https://github.com/varigit/ti-u-boot/commit/81cad3a3c80216244503baac68448371c099b1fe am62x_var_som: Check/apply RGMII_ID quirk at boot time]</li> | ||
<li>[https://github.com/varigit | <li>[https://github.com/varigit/ti-u-boot/commit/c7143c864d96e8764179dae2f7f1c62abeec28d6 am62x_var_som: Add bootarg for rgmii_id_quirk]</li> | ||
</ul> | </ul> | ||
| <ul> | | <ul> | ||
Latest revision as of 09:12, 12 July 2024
VAR-SOM-AM62 changelog
VAR-SOM-AM62 Rev. 1.1A
Hardware Modifications
Removal of RGMII TX CLK delay filters on both Ethernet interfaces
The RGMII spec requires a skew between the clock and data at the receiver. On previous SOM revisions, the delay was introduced on the SOM via an inline filter on the TX (MAC) clk of each Ethernet instance, and the SOC internal RGMII Clock Transmit delay was disabled. The latest AM62 Reference Manual removed the documentation of the option to disable this SOC internal delay. Therefore, starting with this SOM revision, the filters have been replaced by Resistors, and a few SW patches are needed to stop disabling the SOC internal delay. See the Software Modifications section below for more details.
Software Modifications
Variscite is updating all relevant software repositories and recommends impacted users to upgrade to the latest software version or to update their U-Boot, kernel, and meta-layers to the latest commit ID of the branch they are already based on.
The following are the relevant patches: