Revision as of 12:50, 22 February 2024

VAR-SOM-AM62 changelog

VAR-SOM-AM62 Rev. 1.1A

Hardware Modifications

Removal of RGMII TX CLK delay filters on both Ethernet interfaces.

The RGMII spec requires a skew between the clock and data at the receiver. On previous assemblies, the delay was introduced on the SoM via an inline filter on the TX (MAC) clk of each Ethernet instance and the SOC internal RGMII Clock Transmit delay was disabled. The latest AM62 Reference Manual removed the documentation of the option to disable this SOC internal delay. Therefore, the filters have been bypassed starting with this SoM revision and thus require additional software patches for proper Ethernet functionality. See the tables below for more information.

Software Modifications

Variscite is updating all relevant software repositories and recommends impacted users to upgrade to the latest software version or to update their U-Boot, kernel, and meta-layers to the latest commit ID of the branch they are already based on.
The following are the relevant patches:

Release	U-Boot	Kernel	meta-layer(s)
Yocto Dunfell (kernel 5.10.168)	Revert "am65-cpsw-nuss: fix inverted rgmii_id bit" net: ti: am65-cpsw-nuss: Remove incorrect RGMII_ID bit functionality net: ti: am65-cpsw-nuss: Support Variscite RGMII_ID board quirk variscite: am62x_eeprom: Use BIT macros for bits variscite: am62x_eeprom: Add feature bit for RGMII_ID assembly quirk variscite: am62x_eth: Add function to check RGMII_ID quirk from eeprom am62x_var_som: Check/apply RGMII_ID quirk at boot time am62x_var_som: Add bootarg for rgmii_id_quirk	Revert "phy: ti: phy-gmii-sel: fix inverted rgmii_id bit" Revert "phy: ti: phy-gmii-sel: Enable RGMII-ID support for AM654" phy: ti: phy-gmii-sel: Handle RGMI_ID quirk for VAR-SOM-AM62	No relevant changes

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 === Hardware Modifications ===
 ==== Removal of RGMII TX CLK delay filters on both Ethernet interfaces. ====
-The RGMII spec requires a skew between the clock and data at the receiver. The internal TI MAC already has this delay and an unsupported register bit that can be used to disable the delay. On previous assemblies, the delay was introduced on the SoM via an inline filter on the TX (MAC) clk of each Ethernet instance and the internal MAC delay disabled. While this delay control bit is present, its use is now not recommended by TI, and as such, the delay should always be enabled in the MAC. Therefore, the filters have been bypassed starting with this SoM revision and thus require additional software patches for proper Ethernet functionality. See the tables below for more information.
+The RGMII spec requires a skew between the clock and data at the receiver. On previous assemblies, the delay was introduced on the SoM via an inline filter on the TX (MAC) clk of each Ethernet instance and the SOC internal RGMII Clock Transmit delay was disabled. The latest AM62 Reference Manual removed the documentation of the option to disable this SOC internal delay. Therefore, the filters have been bypassed starting with this SoM revision and thus require additional software patches for proper Ethernet functionality. See the tables below for more information.
 === Software Modifications ===

VAR-SOM-AM62 rev changelog: Difference between revisions