VAR-SOM-AM62 rev changelog: Difference between revisions
| Line 18: | Line 18: | ||
| Yocto Dunfell (kernel 5.10.168) | | Yocto Dunfell (kernel 5.10.168) | ||
| <ul> | | <ul> | ||
<li> | <li>[https://github.com/varigit/ti-linux-kernel/commit/bd17d332cda0b80a27d22301598b022ff7d99412 Revert "phy: ti: phy-gmii-sel: fix inverted rgmii_id bit"]</li> | ||
<li>test2</li> | <li>test2</li> | ||
| 123 | | 123 | ||
| meta-variscite-bsp-ti | | meta-variscite-bsp-ti | ||
|} | |} | ||
Revision as of 22:00, 21 February 2024
VAR-SOM-AM62 changelog
VAR-SOM-AM62 (February 2024)
Hardware Modifications
Removal of RGMII TX CLK delay filters on both Ethernet interfaces.
The RGMII spec requires a skew between the clock and data at the receiver. The internal TI MAC already has this delay and an unsupported register bit that can be used to disable the delay. On previous assemblies, the delay was introduced on the SoM via an inline filter on the TX (MAC) clk of each Ethernet instance and the internal MAC delay disabled. While this delay control bit is present, its use is not recommended by TI, and as such, the delay should always be enabled in the MAC. Therefore, the filters have been bypassed starting with this SoM and thus require additional software patches for proper Ethernet functionality. See the tables below for more information.
Software Modifications
Variscite is updating all relevant software repositories and recommends impacted users to upgrade to the latest software version or to update their U-Boot, kernel, and meta-layers to the latest commit ID of the branch they are already based on.
The following are the relevant patches:
| Release | U-Boot | Kernel | meta-layer(s) |
|---|---|---|---|
| Yocto Dunfell (kernel 5.10.168) | 123 | meta-variscite-bsp-ti |