DART-MX8M-PLUS Display: Difference between revisions
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Now we have to force video_pll1_out to provide this specific value (980000000). | Now we have to force video_pll1_out to provide this specific value (980000000). | ||
* we need to update video_pll1_out with this new value in the file arch/arm64/boot/dts/freescale/imx8mp.dtsi | * we need to update video_pll1_out with this new value in the ''clock-controller'' node of the file arch/arm64/boot/dts/freescale/imx8mp.dtsi | ||
* we need to introduce a clock setting providing this value in the file drivers/clk/imx/clk-pll14xx.c | * we need to introduce a clock setting providing this value in the file drivers/clk/imx/clk-pll14xx.c | ||
The structure | The structure imx_pll1443x_tbl provides the following set of values | ||
rate, mdiv, pdiv, sdiv, kdiv | rate, mdiv, pdiv, sdiv, kdiv | ||
| Line 105: | Line 105: | ||
Let's make things easy and assume kdiv = 0 and sdiv = 1. | Let's make things easy and assume kdiv = 0 and sdiv = 1. | ||
In order to get a rate of 980 MHz we can just add the following line (keeping the descending rate order) | In order to get a rate of 980 MHz we can just add the following line in the struct ''imx_pll1443x_tbl'' (keeping the descending rate order) | ||
(980000000U, 245, 3, 1, 0) | (980000000U, 245, 3, 1, 0) | ||
|}} | |}} | ||
Revision as of 22:08, 26 March 2022
HDMI, MIPI-DSI and LVDS
DART-MX8M-PLUS SoC supports LVDS, HDMI and MIPI-DSI interfaces.
DART-MX8M-PLUS carrier board comes with LVDS and HDMI connectors, so you can easily connect LVDS and HDMI displays.
Connecting MIPI-DSI display to DART-MX8M-PLUS carrier board requires designing a custom connector.
Adding custom LVDS panel
DART-MX8M-PLUS evaluation kit comes with 800x480 LCD panel. DART-MX8M-PLUS DTS file was created with this panel in mind.
To support a custom LVDS panel you should make several modifications.
The following code references Variscite panel in arch/arm64/boot/dts/freescale/imx8mp-var-dart.dtb under kernel source tree
panel {
compatible = "sgd,gktw70sdae4se", "panel-lvds";
backlight = <&backlight>;
width-mm = <153>;
height-mm = <87>;
label = "gktw70sdae4se";
data-mapping = "jeida-24";
status = "okay";
panel-timing {
clock-frequency = <33000000>;
hactive = <800>;
vactive = <480>;
hback-porch = <40>;
hfront-porch = <40>;
vback-porch = <29>;
vfront-porch = <13>;
hsync-len = <48>;
vsync-len = <3>;
hsync-active = <0>;
vsync-active = <0>;
de-active = <1>;
};
...
};
&ldb {
status = "okay";
lvds-channel@0 {
fsl,data-mapping = "jeida";
fsl,data-width = <24>;
status = "okay";
...
};
You should modify panel "data-mapping" and "display-timings" properties to match your panel specification.
You should also modify ldb (internal LVDS bridge) "fsl,data-mapping" and "fsl,data-width" properties to match your panel specification.
Supported "data-mapping" values are "jeida-18", "jeida-24" and "vesa-24".
Supported "fsl,data-mapping" values are "jeida", and "spwg".
Supported "fsl,data-width" values are <18>, and <24>.
For dual channel LVDS panels add fsl,dual-channel property to ldb node, as in the example below:
&ldb {
status = "okay";
fsl,dual-channel;
lvds-channel@0 {
fsl,data-mapping = "jeida";
fsl,data-width = <24>;
status = "okay";
...
};