DART-6UL SPI: Difference between revisions

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{{PageHeader|DART-6UL- SPI}} {{DocImage|category1=DART-6UL|category2=Yocto}} __toc__
{{PageHeader|DART-6UL/VAR-SOM-MX7 - SPI}} {{DocImage|category1=Yocto|category2=Debian}}[[category:DART-6UL]][[Category:VAR-SOM-MX7]] __toc__
In this example we will show how to configure SPI 1 and SPI 2 to work on SOM
In this example we will show how to configure SPI 1 and SPI 2 to work on SOM
= Kernel configuration=
= Kernel configuration=
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* In menuconfig: Device Drivers -> SPI support -> <*>  User mode SPI device driver support<br>
* In menuconfig: Device Drivers -> SPI support -> <*>  User mode SPI device driver support<br>


=SPI 1=
= SPI 1 on 6UL Custom Board and Condcerto Board =
== Add spidev to your device tree ==
== Add spidev to your device tree ==
<pre>
<pre>
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         chip1: spidev@0 {
         chip1: spidev@0 {
               compatible = "spidev";
               compatible = "var,spidev";
               spi-max-frequency = <12000000>;
               spi-max-frequency = <12000000>;
               reg = <0>;
               reg = <0>;
Line 26: Line 26:
<pre>
<pre>
&iomuxc {
&iomuxc {
imx6ul-evk {
pinctrl_ecspi1_1: ecspi1grp {
pinctrl_ecspi1_1: ecspi1grp {
fsl,pins = <
fsl,pins = <
MX6UL_PAD_CSI_DATA07__ECSPI1_MISO      0x100b1
MX6UL_PAD_CSI_DATA07__ECSPI1_MISO      0x100b1
MX6UL_PAD_CSI_DATA06__ECSPI1_MOSI      0x100b1
MX6UL_PAD_CSI_DATA06__ECSPI1_MOSI      0x100b1
MX6UL_PAD_CSI_DATA04__ECSPI1_SCLK      0x100b1
MX6UL_PAD_CSI_DATA04__ECSPI1_SCLK      0x100b1
MX6UL_PAD_CSI_DATA05__GPIO4_IO26        0x100b1
MX6UL_PAD_CSI_DATA05__GPIO4_IO26        0x100b1
>;
>;
};
};
};
};
};
</pre>
</pre>
== Pins on the boards ==
{| class="wikitable"
|-
! scope="col"| pins
! scope="col"| 6UL Custom Board
! scope="col"| Concerto Board
|-
! scope="row"| MISO
| J11.8
| J14.2
|-
! scope="row"| MOSI
| J11.6
| J14.1
|-
! scope="row"| SCLK
| J11.2
| J14.4
|-
! scope="row"| chipselect
| J11.4
| J14.6
|}
Note: The pins here were set arbitrarily. You should set them based on your hardware design, and make sure they are not conflicting with other devices in the device tree.<br>  you can also have multiple chip selects.<br>
Note: The pins here were set arbitrarily. You should set them based on your hardware design, and make sure they are not conflicting with other devices in the device tree.<br>  you can also have multiple chip selects.<br>
= SPI 2 =
 
= SPI 2 on 6UL Custom Board =
== Add spidev to your device tree ==
== Add spidev to your device tree ==
<pre>
<pre>
Line 50: Line 74:


spidev@0 {
spidev@0 {
               compatible = "spidev";
               compatible = "var,spidev";
              spi-max-frequency = <12000000>;
              reg = <0>;
        };
};
</pre>
== Add pin control to your device tree ==
<pre>
&iomuxc {
pinctrl_ecspi2_1: ecspi2grp {
fsl,pins = <
MX6UL_PAD_CSI_DATA03__ECSPI2_MISO 0x100b1 /* from J13.2 */
MX6UL_PAD_CSI_DATA02__ECSPI2_MOSI 0x100b1 /* from J6.7 */
MX6UL_PAD_CSI_DATA00__ECSPI2_SCLK 0x100b1 /* from J11.9 */
MX6UL_PAD_CSI_DATA01__GPIO4_IO22 0x100b1 /* from J6.5 */
>;
};
};
</pre>
Note: The pins here were set arbitrarily. You should set them based on your hardware design, and make sure they are not conflicting with other devices in the device tree.<br>  you can also have multiple chip selects.<br>
 
= SPI 2 on Concerto Board =
== Add spidev to your device tree ==
<pre>
&ecspi2 {
fsl,spi-num-chipselects = <1>;
cs-gpios = <&gpio1 29 0>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_ecspi2_1>;
status = "okay";
 
spidev@0 {
              compatible = "var,spidev";
              spi-max-frequency = <12000000>;
              reg = <0>;
        };
};
</pre>
== Add pin control to your device tree ==
<pre>
&iomuxc {
pinctrl_ecspi2_1: ecspi2grp {
fsl,pins = <
MX6UL_PAD_UART5_TX_DATA__ECSPI2_MOSI 0x100b1 /* from J18.12 */
MX6UL_PAD_UART5_RX_DATA__ECSPI2_MISO 0x100b1 /* from J18.17 */
MX6UL_PAD_UART4_TX_DATA__ECSPI2_SCLK 0x100b1 /* from J18.18 */
MX6UL_PAD_UART4_RX_DATA__GPIO1_IO29 0x100b1 /* from J18.11 */
>;
};
};
</pre>
Note: The pins here were set arbitrarily. You should set them based on your hardware design, and make sure they are not conflicting with other devices in the device tree.<br>  you can also have multiple chip selects.<br>
 
= SPI 4 on Symphony Board (ENET2 not enabled) =
== Add spidev to your device tree ==
<pre>
&ecspi4 {
fsl,spi-num-chipselects = <1>;
cs-gpios = <&gpio2 15 0>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_ecspi4>;
status = "okay";
 
spidev@0 {
              compatible = "var,spidev";
               spi-max-frequency = <12000000>;
               spi-max-frequency = <12000000>;
               reg = <0>;
               reg = <0>;
Line 59: Line 147:
<pre>
<pre>
&iomuxc {
&iomuxc {
imx6ul-evk {
pinctrl_ecspi4: ecspi4grp {
pinctrl_ecspi2_1: ecspi2grp {
fsl,pins = <
fsl,pins = <
MX6UL_PAD_ENET2_TX_EN__ECSPI4_MOSI 0x100b1 /* from J16.8 */
MX6UL_PAD_CSI_DATA03__ECSPI2_MISO 0x100b1
MX6UL_PAD_ENET2_TX_CLK__ECSPI4_MISO 0x100b1 /* from J16.6 */
MX6UL_PAD_CSI_DATA02__ECSPI2_MOSI 0x100b1
MX6UL_PAD_ENET2_TX_DATA1__ECSPI4_SCLK 0x100b1 /* from J16.2 */
MX6UL_PAD_CSI_DATA00__ECSPI2_SCLK 0x100b1
MX6UL_PAD_ENET2_RX_ER__GPIO2_IO15 0x100b1 /* from J16.4 */
MX6UL_PAD_CSI_DATA01__GPIO4_IO22 0x100b1
>;
>;
};
};
};
};
};
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Compile the kernel and device tree and update the SOM.
Compile the kernel and device tree and update the SOM.
= Testing =
= Testing =
There's an SPI testing utility C code example in the Documentation folder of the kernel source tree: Documentation/spi/spidev_test.c<br>
There's an SPI testing utility C code example in the kernel source tree: tools/spi/spidev_test.c (in older kernels: Documentation/spi/spidev_test.c)<br>
To cross compile it use the following command
To cross compile it use the following command:
<pre>
$ $CC ./tools/spi/spidev_test.c -o ./spidev_test
$ $CC ./Documentation/spi/spidev_test.c -o ./spidev_test
</pre>
 
== SPI 1 ==
SPI 1 will be accessible on the following EVK pins:
* J11.2 - SPI1.CLK
* J11.6 - SPI1.MISO
* J11.8 - SPI1.MOSI
* J11.4 - SPI1.SS0


== SPI 2 ==
On the target, for a test transmission, you can run the command
SPI 2 will be accessible on the following EVK pins:
root@imx6ul-var-dart:~# spidev_test -D /dev/spidevM.N
* J11.9 - SPI2.CLK
where
* J13.2 - SPI2.MISO
* M is the spi bus index (0 for ecspi1, 1 for ecspi2, ...)
* J6.7 - SPI2.MOSI
* N is the chip select index (0 for the 1st chipselect, 1 for the 2nd chipselect, ...)
* J6.5  - SPI2.SS0
For a test loopback, you can short MISO and MOSI pins and run
root@imx6ul-var-dart:~# echo "SPI test packet" > /tmp/SPI.in && echo "" > /tmp/SPI.out
  root@imx6ul-var-dart:~# spidev_test -v -D /dev/spidevM.N-v -i /tmp/SPI.in -o /tmp/SPI.out
The SPI.in file will be used as test packet, sent over SPI, and the received bytes will be stored in the SPI.out file: SPI.in and SPI.out will match.

Latest revision as of 19:27, 28 April 2023

DART-6UL/VAR-SOM-MX7 - SPI

In this example we will show how to configure SPI 1 and SPI 2 to work on SOM

Kernel configuration

Verify that the User mode SPI driver (CONFIG_SPI_SPIDEV) is enabled in your kernel configuration:

  • In menuconfig: Device Drivers -> SPI support -> <*> User mode SPI device driver support

SPI 1 on 6UL Custom Board and Condcerto Board

Add spidev to your device tree

&ecspi1 {
	fsl,spi-num-chipselects = <1>;
	cs-gpios = <&gpio4 26 0>;
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_ecspi1_1>;
	status = "okay";

        chip1: spidev@0 {
               compatible = "var,spidev";
               spi-max-frequency = <12000000>;
               reg = <0>;
        };
};

Add pin control to your device tree

&iomuxc {
	pinctrl_ecspi1_1: ecspi1grp {
		fsl,pins = <
			MX6UL_PAD_CSI_DATA07__ECSPI1_MISO       0x100b1
			MX6UL_PAD_CSI_DATA06__ECSPI1_MOSI       0x100b1
			MX6UL_PAD_CSI_DATA04__ECSPI1_SCLK       0x100b1
			MX6UL_PAD_CSI_DATA05__GPIO4_IO26        0x100b1
		>;
	};

};

Pins on the boards

pins 6UL Custom Board Concerto Board
MISO J11.8 J14.2
MOSI J11.6 J14.1
SCLK J11.2 J14.4
chipselect J11.4 J14.6

Note: The pins here were set arbitrarily. You should set them based on your hardware design, and make sure they are not conflicting with other devices in the device tree.
you can also have multiple chip selects.

SPI 2 on 6UL Custom Board

Add spidev to your device tree

&ecspi2 {
	fsl,spi-num-chipselects = <1>;
	cs-gpios = <&gpio4 22 0>;
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_ecspi2_1>;
	status = "okay";

	spidev@0 {
               compatible = "var,spidev";
               spi-max-frequency = <12000000>;
               reg = <0>;
        };
};

Add pin control to your device tree

&iomuxc {
	pinctrl_ecspi2_1: ecspi2grp {
		fsl,pins = <
			MX6UL_PAD_CSI_DATA03__ECSPI2_MISO	0x100b1 /* from J13.2 */
			MX6UL_PAD_CSI_DATA02__ECSPI2_MOSI	0x100b1 /* from J6.7 */
			MX6UL_PAD_CSI_DATA00__ECSPI2_SCLK	0x100b1 /* from J11.9 */
			MX6UL_PAD_CSI_DATA01__GPIO4_IO22	0x100b1 /* from J6.5 */
		>;
	};
};

Note: The pins here were set arbitrarily. You should set them based on your hardware design, and make sure they are not conflicting with other devices in the device tree.
you can also have multiple chip selects.

SPI 2 on Concerto Board

Add spidev to your device tree

&ecspi2 {
	fsl,spi-num-chipselects = <1>;
	cs-gpios = <&gpio1 29 0>;
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_ecspi2_1>;
	status = "okay";

	spidev@0 {
               compatible = "var,spidev";
               spi-max-frequency = <12000000>;
               reg = <0>;
        };
};

Add pin control to your device tree

&iomuxc {
	pinctrl_ecspi2_1: ecspi2grp {
		fsl,pins = <
			MX6UL_PAD_UART5_TX_DATA__ECSPI2_MOSI	0x100b1 /* from J18.12 */
			MX6UL_PAD_UART5_RX_DATA__ECSPI2_MISO	0x100b1 /* from J18.17 */
			MX6UL_PAD_UART4_TX_DATA__ECSPI2_SCLK	0x100b1 /* from J18.18 */
			MX6UL_PAD_UART4_RX_DATA__GPIO1_IO29	0x100b1 /* from J18.11 */
		>;
	};
};

Note: The pins here were set arbitrarily. You should set them based on your hardware design, and make sure they are not conflicting with other devices in the device tree.
you can also have multiple chip selects.

SPI 4 on Symphony Board (ENET2 not enabled)

Add spidev to your device tree

&ecspi4 {
	fsl,spi-num-chipselects = <1>;
	cs-gpios = <&gpio2 15 0>;
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_ecspi4>;
	status = "okay";

	spidev@0 {
               compatible = "var,spidev";
               spi-max-frequency = <12000000>;
               reg = <0>;
        };
};

Add pin control to your device tree

&iomuxc {
	pinctrl_ecspi4: ecspi4grp {
		fsl,pins = <
			MX6UL_PAD_ENET2_TX_EN__ECSPI4_MOSI	0x100b1 /* from J16.8 */
			MX6UL_PAD_ENET2_TX_CLK__ECSPI4_MISO	0x100b1 /* from J16.6 */
			MX6UL_PAD_ENET2_TX_DATA1__ECSPI4_SCLK	0x100b1 /* from J16.2 */
			MX6UL_PAD_ENET2_RX_ER__GPIO2_IO15	0x100b1 /* from J16.4 */
		>;
	};
};

Note: The pins here were set arbitrarily. You should set them based on your hardware design, and make sure they are not conflicting with other devices in the device tree.
you can also have multiple chip selects.

Compile

Compile the kernel and device tree and update the SOM.

Testing

There's an SPI testing utility C code example in the kernel source tree: tools/spi/spidev_test.c (in older kernels: Documentation/spi/spidev_test.c)
To cross compile it use the following command:

$ $CC ./tools/spi/spidev_test.c -o ./spidev_test

On the target, for a test transmission, you can run the command

root@imx6ul-var-dart:~# spidev_test -D /dev/spidevM.N

where

  • M is the spi bus index (0 for ecspi1, 1 for ecspi2, ...)
  • N is the chip select index (0 for the 1st chipselect, 1 for the 2nd chipselect, ...)

For a test loopback, you can short MISO and MOSI pins and run

root@imx6ul-var-dart:~# echo "SPI test packet" > /tmp/SPI.in && echo "" > /tmp/SPI.out
root@imx6ul-var-dart:~# spidev_test -v -D /dev/spidevM.N-v -i /tmp/SPI.in -o /tmp/SPI.out

The SPI.in file will be used as test packet, sent over SPI, and the received bytes will be stored in the SPI.out file: SPI.in and SPI.out will match.