VAR-SOM-MX7 Ethernet

VAR-SOM-MX7 - Ethernet

There are two 1Gigabit Ethernet ports on the kit, ETH1 and ETH2.

To run a performance test:
iperf3 server (on Target/Host):

$ ifconfig  (to get the IP address)
$ iperf3 -s

iperf3 client (on Host/Target):

$ iperf3 -c <IP_ADDRESS_OF_IPERF_SERVER> -u -b 1000M

Using only one Ethernet port

Note: You can follow the "Build Linux from source code" guide to get the Linux kernel source, apply one of the below patches, build only the device trees and copy them to your SD card.

Removing the second Ethernet port

Apply the following patch to the Linux kernel source, for removing the second Ethernet port only:

--- a/arch/arm/boot/dts/imx7d-var-som.dtsi
+++ b/arch/arm/boot/dts/imx7d-var-som.dtsi
@@ -255,29 +255,9 @@
                        compatible = "ethernet-phy-ieee802.3-c22";
                        reg = <0>;
                };
-
-               ethphy1: ethernet-phy@1 {
-                       compatible = "ethernet-phy-ieee802.3-c22";
-                       reg = <1>;
-               };
        };
 };
 
-&fec2 {
-       pinctrl-names = "default";
-       pinctrl-0 = <&pinctrl_enet2>;
-
-       assigned-clocks = <&clks IMX7D_ENET2_TIME_ROOT_SRC>,
-                         <&clks IMX7D_ENET2_TIME_ROOT_CLK>;
-       assigned-clock-parents = <&clks IMX7D_PLL_ENET_MAIN_100M_CLK>;
-       assigned-clock-rates = <0>, <100000000>;
-       phy-mode = "rgmii";
-       phy-handle = <&ethphy1>;
-       phy-reset-gpios = <&gpio4 3 GPIO_ACTIVE_LOW>;
-       fsl,magic-packet;
-       status = "okay";
-};
-
 &mipi_csi {
        clock-frequency = <240000000>;
        status = "okay";
@@ -494,7 +474,6 @@
                                MX7D_PAD_GPIO1_IO14__GPIO1_IO14         0x80000000  /* bt reg on */
                                MX7D_PAD_EPDC_PWR_COM__GPIO2_IO30       0x80000000  /* capacitive touch irq */
                                MX7D_PAD_SD2_RESET_B__GPIO5_IO11        0x59  /* ethphy0 reset */
-                               MX7D_PAD_UART2_TX_DATA__GPIO4_IO3       0x59  /* ethphy1 reset */
                                MX7D_PAD_GPIO1_IO10__GPIO1_IO10         0x59  /* hsic hub reset */
                                MX7D_PAD_GPIO1_IO12__GPIO1_IO12         0x59  /* hsic hub connect */
                                MX7D_PAD_GPIO1_IO13__GPIO1_IO13         0x59  /* LED */
@@ -568,23 +547,6 @@
                        >;
                };
 
-               pinctrl_enet2: enet2grp {
-                       fsl,pins = <
-                               MX7D_PAD_EPDC_GDSP__ENET2_RGMII_TXC             0x1
-                               MX7D_PAD_EPDC_SDCE2__ENET2_RGMII_TD0            0x1
-                               MX7D_PAD_EPDC_SDCE3__ENET2_RGMII_TD1            0x1
-                               MX7D_PAD_EPDC_GDCLK__ENET2_RGMII_TD2            0x1
-                               MX7D_PAD_EPDC_GDOE__ENET2_RGMII_TD3             0x1
-                               MX7D_PAD_EPDC_GDRL__ENET2_RGMII_TX_CTL          0x1
-                               MX7D_PAD_EPDC_SDCE1__ENET2_RGMII_RXC            0x1
-                               MX7D_PAD_EPDC_SDCLK__ENET2_RGMII_RD0            0x1
-                               MX7D_PAD_EPDC_SDLE__ENET2_RGMII_RD1             0x1
-                               MX7D_PAD_EPDC_SDOE__ENET2_RGMII_RD2             0x1
-                               MX7D_PAD_EPDC_SDSHR__ENET2_RGMII_RD3            0x1
-                               MX7D_PAD_EPDC_SDCE0__ENET2_RGMII_RX_CTL         0x1
-                       >;
-               };
-
                pinctrl_flexcan2: flexcan2grp {
                        fsl,pins = <
                                MX7D_PAD_I2C3_SCL__FLEXCAN2_RX          0x59

Removing the first Ethernet port

Apply the following patch to the Linux kernel source, for removing the first Ethernet port only:

--- a/arch/arm/boot/dts/imx7d-var-som.dtsi
+++ b/arch/arm/boot/dts/imx7d-var-som.dtsi
@@ -255,41 +255,6 @@
 	};
 };
 
-&fec1 {
-	pinctrl-names = "default";
-	pinctrl-0 = <&pinctrl_enet1>;
-	phy-supply=<&vgen3_reg>;
-	assigned-clocks = <&clks IMX7D_ENET_PHY_REF_ROOT_SRC>,
-			  <&clks IMX7D_ENET_AXI_ROOT_SRC>,
-			  <&clks IMX7D_ENET1_TIME_ROOT_SRC>,
-			  <&clks IMX7D_ENET1_TIME_ROOT_CLK>,
-			  <&clks IMX7D_ENET_AXI_ROOT_CLK>;
-	assigned-clock-parents = <&clks IMX7D_PLL_ENET_MAIN_25M_CLK>,
-				 <&clks IMX7D_PLL_ENET_MAIN_250M_CLK>,
-				 <&clks IMX7D_PLL_ENET_MAIN_100M_CLK>;
-	assigned-clock-rates = <0>, <0>, <0>, <100000000>, <250000000>;
-	phy-mode = "rgmii-id";
-	phy-handle = <&ethphy0>;
-	phy-reset-gpios = <&gpio5 11 GPIO_ACTIVE_LOW>;
-	fsl,magic-packet;
-	status = "okay";
-
-	mdio {
-		#address-cells = <1>;
-		#size-cells = <0>;
-
-		ethphy0: ethernet-phy@0 {
-			compatible = "ethernet-phy-ieee802.3-c22";
-			reg = <0>;
-		};
-
-		ethphy1: ethernet-phy@1 {
-			compatible = "ethernet-phy-ieee802.3-c22";
-			reg = <1>;
-		};
-	};
-};
-
 &fec2 {
 	pinctrl-names = "default";
 	pinctrl-0 = <&pinctrl_enet2>;
@@ -308,6 +273,16 @@
 	phy-reset-gpios = <&gpio4 3 GPIO_ACTIVE_LOW>;
 	fsl,magic-packet;
 	status = "okay";
+
+	mdio {
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		ethphy1: ethernet-phy@1 {
+			compatible = "ethernet-phy-ieee802.3-c22";
+			reg = <1>;
+		};
+	};
 };
 
 &mipi_csi {
@@ -504,7 +479,6 @@
 			fsl,pins = <
 				MX7D_PAD_GPIO1_IO14__GPIO1_IO14		0x80000000  /* bt reg on */
 				MX7D_PAD_EPDC_PWR_COM__GPIO2_IO30	0x80000000  /* capacitive touch irq */
-				MX7D_PAD_SD2_RESET_B__GPIO5_IO11	0x59  /* ethphy0 reset */
 				MX7D_PAD_UART2_TX_DATA__GPIO4_IO3	0x59  /* ethphy1 reset */
 				MX7D_PAD_GPIO1_IO10__GPIO1_IO10		0x59  /* hsic hub reset */
 				MX7D_PAD_GPIO1_IO12__GPIO1_IO12		0x59  /* hsic hub connect */
@@ -560,27 +534,10 @@
 			>;
 		};
 
-		pinctrl_enet1: enet1grp {
-			fsl,pins = <
-				MX7D_PAD_SD2_CD_B__ENET1_MDIO			0x3
-				MX7D_PAD_SD2_WP__ENET1_MDC			0x3
-				MX7D_PAD_ENET1_RGMII_TXC__ENET1_RGMII_TXC	0x1
-				MX7D_PAD_ENET1_RGMII_TD0__ENET1_RGMII_TD0	0x1
-				MX7D_PAD_ENET1_RGMII_TD1__ENET1_RGMII_TD1	0x1
-				MX7D_PAD_ENET1_RGMII_TD2__ENET1_RGMII_TD2	0x1
-				MX7D_PAD_ENET1_RGMII_TD3__ENET1_RGMII_TD3	0x1
-				MX7D_PAD_ENET1_RGMII_TX_CTL__ENET1_RGMII_TX_CTL	0x1
-				MX7D_PAD_ENET1_RGMII_RXC__ENET1_RGMII_RXC	0x1
-				MX7D_PAD_ENET1_RGMII_RD0__ENET1_RGMII_RD0	0x1
-				MX7D_PAD_ENET1_RGMII_RD1__ENET1_RGMII_RD1	0x1
-				MX7D_PAD_ENET1_RGMII_RD2__ENET1_RGMII_RD2	0x1
-				MX7D_PAD_ENET1_RGMII_RD3__ENET1_RGMII_RD3	0x1
-				MX7D_PAD_ENET1_RGMII_RX_CTL__ENET1_RGMII_RX_CTL	0x1
-			>;
-		};
-
 		pinctrl_enet2: enet2grp {
 			fsl,pins = <
+				MX7D_PAD_SD2_CD_B__ENET2_MDIO			0x3
+				MX7D_PAD_SD2_WP__ENET2_MDC			0x3
 				MX7D_PAD_EPDC_GDSP__ENET2_RGMII_TXC		0x1
 				MX7D_PAD_EPDC_SDCE2__ENET2_RGMII_TD0		0x1
 				MX7D_PAD_EPDC_SDCE3__ENET2_RGMII_TD1		0x1