AM62 SPI

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VAR-SOM-AM62 SPI

In this example we will show how to configure and test SPI1 on VAR-SOM-AM62. The SPI pins on external connector J16 are used for SPI loopback test.

Kernel configuration

Verify that the OMAP24XX SPI driver (CONFIG_SPI_OMAP24XX) is enabled in your kernel configuration:

• In menuconfig: Device Drivers -> SPI support -> <*> McSPI driver for OMAP
  

Verify that the User mode SPI driver (CONFIG_SPI_SPIDEV) is enabled in your kernel configuration:

• In menuconfig: Device Drivers -> SPI support -> <*> User mode SPI device driver support
  

Device Tree configuration

On the VAR-SOM-AM62, main_spi2 is configured with a spidev device that can be used to test SPI. The following steps demonstrate how to test spidev.

Add spidev node

Edit /arch/arm64/boot/dts/ti/k3-am625-var-som-symphony.dts to modify the cs-gpios spidev node.
GPIO1_13 will be used in this example to control SPI CS0.

&main_spi2 {
	pinctrl-names = "default";
	pinctrl-0 = <&main_spi2_pins_default>;
	ti,pindir-d0-out-d1-in = <1>;
	cs-gpios = <&main_gpio1 13 0>;

	spidev@0 {
		compatible = "var,spidev";
		reg = <0>;
		spi-max-frequency = <12000000>;
		status = "okay";
	};
};

Configure SPI2 pins

Configure SPI2 pin and pad settings:

&main_pmx0 {
	...
	main_spi2_pins_default: main_spi2-pins-default {
		pinctrl-single,pins = <
			AM62X_IOPAD(0x01b0, PIN_INPUT, 1) /* (A20) MCASP0_ACLKR.SPI2_CLK */
			AM62X_IOPAD(0x0194, PIN_OUTPUT, 1) /* (B19) MCASP0_AXR3.SPI2_D0 */
			AM62X_IOPAD(0x0198, PIN_INPUT, 1) /* (A19) MCASP0_AXR2.SPI2_D1 */
			AM62X_IOPAD(0x01ac, PIN_OUTPUT, 7) /* (E19) MCASP0_AFSR.GPIO1_13 */
		>;
	};
	...
};

Recompile the kernel

Compile the kernel (only if kernel configuration was changed) and device tree and update the SOM.

Compile SPI test application

There's an SPI test utility in the kernel source tree: tools/spi/spidev_test.c
To cross compile it, use the following command:

$ $CC ./tools/spi/spidev_test.c -o ./spidev_test

SPI 1 External Connector

SPI 2 will be accessible on the following EVK pins:

• J16.2 - SPI1.SCLK
• J16.4 - SPI1.SS0
• J16.6 - SPI1.MOSI
• J16.8 - SPI1.MISO

Run SPI Test

Copy spidev_test binary to VAR-SOM-AM62.
Loop SPI1.MOSI and SPI1.MISO by putting a jumper on J16.6 and J16.8

Run SPI test tool

# ./spidev_test -v -D /dev/spidev5.0 

The output of successful test should look like this:

spi mode: 0x20
bits per word: 8
max speed: 500000 Hz (500 KHz)
TX | FF FF FF FF FF FF 40 00 00 00 00 95 FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF F0 0D  | ......@....�..................�.
RX | FF FF FF FF FF FF 40 00 00 00 00 95 FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF F0 0D  | ......@....�..................�.

Using multiple SPI CS lines

AM625 SPI controllers support up to 2 chip select lines.

In the example below GPIO1_13 and GPIO1_29 are used to control CS0 and CS1 respectively.
When selecting CS GPIO pins make sure they are not used to control other peripherals.

&main_spi2 {
	pinctrl-names = "default";
	pinctrl-0 = <&main_spi2_pins_default>;
	ti,pindir-d0-out-d1-in = <1>;
	cs-gpios = <&main_gpio1 13 0>, <&main_gpio0 29 0>;

	chip@0 {
		reg = <0>;
		...
	};

	chip@1 {
		reg = <1>;
		...
	};
};

&main_pmx0 {
	...
	main_spi2_pins_default: main_spi2-pins-default {
		pinctrl-single,pins = <
			AM62X_IOPAD(0x01b0, PIN_INPUT, 1) /* (A20) MCASP0_ACLKR.SPI2_CLK */
			AM62X_IOPAD(0x0194, PIN_OUTPUT, 1) /* (B19) MCASP0_AXR3.SPI2_D0 */
			AM62X_IOPAD(0x0198, PIN_INPUT, 1) /* (A19) MCASP0_AXR2.SPI2_D1 */
			AM62X_IOPAD(0x01ac, PIN_OUTPUT, 7) /* (E19) MCASP0_AFSR.GPIO1_13 */
			AM62X_IOPAD(0x0074, PIN_OUTPUT, 7) /* (U25) GPMC0_AD14.GPIO0_29 */
		>;
	};
	...
};