DART-MX8M SPI: Difference between revisions
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--> {{PageHeader|{{#var:HARDWARE_NAME}} SPI}} {{DocImage|category1=Yocto|category2=Android}}[[Category:Debian]][[Category:DART-MX8M]][[Category:DART-MX8M-MINI]][[Category:DART-MX8M-PLUS]]__toc__ | --> {{PageHeader|{{#var:HARDWARE_NAME}} SPI}} {{DocImage|category1=Yocto|category2=Android}}[[Category:Debian]][[Category:DART-MX8M]][[Category:DART-MX8M-MINI]][[Category:DART-MX8M-PLUS]]__toc__ | ||
<!-- Set local variables | <!-- Set local variables | ||
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= Device Tree configuration = | = Device Tree configuration = | ||
{{#switch: {{#var:HARDWARE_NAME}} | |||
| VAR-SOM-MX93= | |||
On the {{#var:HARDWARE_NAME}}, lpspi6 is configured with a spidev device that can be used to test SPI. | |||
The following steps demonstrate how to test spidev. | |||
| DART-MX95= | |||
On the {{#var:HARDWARE_NAME}}, lpspi7 is configured with a spidev device that can be used to test SPI. | |||
The following steps demonstrate how to test spidev. | |||
| #default= | |||
The default {{#var:HARDWARE_NAME}} SPI configuration is for resistive touch controller on CS0. | The default {{#var:HARDWARE_NAME}} SPI configuration is for resistive touch controller on CS0. | ||
For the purpose of loop back test the configuration should be modified to use a different CS line. | For the purpose of loop back test the configuration should be modified to use a different CS line. | ||
}} | |||
== Add spidev node == | == Add spidev node == | ||
Line 124: | Line 134: | ||
spi-max-frequency = <1000000>; | spi-max-frequency = <1000000>; | ||
status = "okay"; | status = "okay"; | ||
}; | |||
}; | |||
</pre> | |||
| DART-MX95= | |||
{{#ifeq: {{#var:ANDROID_NAME}} | Pie |{{#var:BUILD_FOLDER}}/{{#var:BUILD_FOLDER_ANDROID}}/variscite/kernel_imx/}}/arch/arm64/boot/dts/freescale/{{#var:DEFAULT_DTS}} provides an enabled spidev node.<br> | |||
GPIO5_4 is used to control SPI CS2 (J25.2 on DT8MCB Carrier) | |||
<pre> | |||
&lpspi7 { | |||
fsl,spi-num-chipselects = <3>; | |||
pinctrl-names = "default", "sleep"; | |||
pinctrl-0 = <&pinctrl_lpspi7>; | |||
pinctrl-1 = <&pinctrl_lpspi7>; | |||
cs-gpios = <&gpio2 14 GPIO_ACTIVE_LOW>, | |||
<&gpio5 13 GPIO_ACTIVE_LOW>, | |||
<&gpio5 4 GPIO_ACTIVE_LOW>; | |||
status = "okay"; | |||
/* Resistive touch controller */ | |||
ads7846@0 { | |||
...... | |||
status = "okay"; | |||
}; | |||
can0: can@1 { | |||
...... | |||
status = "okay"; | |||
}; | |||
spidev0: spi@2 { | |||
reg = <2>; | |||
compatible = "lwn,bk4"; | |||
spi-max-frequency = <1000000>; | |||
}; | }; | ||
}; | }; | ||
Line 216: | Line 259: | ||
}; | }; | ||
</pre> | </pre> | ||
| DART-MX95= | |||
Already configured in the default device tree file | |||
|}} | |}} | ||
Line 239: | Line 284: | ||
SPI 1 will be accessible on the following EVK pins: | SPI 1 will be accessible on the following EVK pins: | ||
* J16.2 - SPI1.SCLK | * J16.2 - SPI1.SCLK | ||
{{#switch: {{#var:HARDWARE_NAME}} | |||
| DART-MX95= | |||
* J25.2 - SAI1_RXFS | |||
| #default= | |||
* J16.4 - SPI1.SS0 | * J16.4 - SPI1.SS0 | ||
}} | |||
* J16.6 - SPI1.MOSI | * J16.6 - SPI1.MOSI | ||
* J16.8 - SPI1.MISO | * J16.8 - SPI1.MISO | ||
Line 246: | Line 296: | ||
Copy spidev_test binary to DART-MX8M.<br> | Copy spidev_test binary to DART-MX8M.<br> | ||
Loop SPI1.MOSI and SPI1.MISO by putting a jumper on J16.6 and J16.8<br> | Loop SPI1.MOSI and SPI1.MISO by putting a jumper on J16.6 and J16.8<br> | ||
{{#switch: {{#var:HARDWARE_NAME}} | {{#switch: {{#var:HARDWARE_NAME}} | ||
| VAR-SOM-MX8M-NANO= | | VAR-SOM-MX8M-NANO= | ||
Configure GPIO1_14 (the default CS0 pin) as output with value 1 to prevent it from interfering with new CS0 pin | |||
<pre> | <pre> | ||
# echo 14 > /sys/class/gpio/export | # echo 14 > /sys/class/gpio/export | ||
Line 255: | Line 304: | ||
# echo 1 > /sys/class/gpio/gpio14/value | # echo 1 > /sys/class/gpio/gpio14/value | ||
</pre> | </pre> | ||
| VAR-SOM-MX93= | |||
| #default= | | #default= | ||
Configure GPIO5_9 (the default CS0 pin) as output with value 1 to prevent it from interfering with new CS0 pin | |||
<pre> | <pre> | ||
# echo 137 > /sys/class/gpio/export | # echo 137 > /sys/class/gpio/export | ||
Line 267: | Line 318: | ||
<pre> | <pre> | ||
# ./spidev_test -v -D /dev/spidev32766.0 | # ./spidev_test -v -D /dev/spidev32766.0 | ||
</pre> | |||
| | |||
{{#ifeq: {{#var:HARDWARE_NAME}} | DART-MX95 | | |||
<pre> | |||
# ./spidev_test -v -D /dev/spidev0.2 | |||
</pre> | </pre> | ||
| | | | ||
<pre> | <pre> | ||
# ./spidev_test -v -D /dev/spidev0.0 | # ./spidev_test -v -D /dev/spidev0.0 | ||
</pre> | </pre> | ||
}} | }}}} | ||
The output of successful test should look like this: | The output of successful test should look like this: | ||
<pre> | <pre> | ||
Line 283: | Line 340: | ||
= Using multiple SPI CS lines = | = Using multiple SPI CS lines = | ||
The i.MX8M SPI controllers support up to 4 chip select lines.<br> | The {{#switch: {{#var:SOC_FAMILY}} | ||
In the example below GPIO1_12 and GPIO1_15 are used to control CS0 and CS1 respectively.<br> | |imx9=i.MX9 SPI controllers support up to 2 chip select lines. | ||
|imx8m|#default=i.MX8M SPI controllers support up to 4 chip select lines. | |||
}} | |||
<br>In the example below GPIO1_12 and GPIO1_15 are used to control CS0 and CS1 respectively.<br> | |||
When selecting CS GPIO pins make sure they are not used to control other peripherals. | When selecting CS GPIO pins make sure they are not used to control other peripherals. | ||
Line 297: | Line 357: | ||
cs-gpios = <&gpio1 0 0>, | cs-gpios = <&gpio1 0 0>, | ||
<&gpio1 1 0>; | <&gpio1 1 0>; | ||
fsl,spi-num-chipselects = <2>; | |||
status = "okay"; | |||
chip1@0 { | |||
reg = <0>; | |||
... | |||
}; | |||
chip2@1 { | |||
reg = <1>; | |||
... | |||
}; | |||
}; | |||
</pre> | |||
|#VAR-SOM-MX93= | |||
<pre> | |||
&lpspi6 { | |||
pinctrl-names = "default"; | |||
pinctrl-0 = <&pinctrl_lpspi6>; | |||
cs-gpios = <&gpio1 12 0>, | |||
<&gpio1 15 0>; | |||
fsl,spi-num-chipselects = <2>; | fsl,spi-num-chipselects = <2>; | ||
status = "okay"; | status = "okay"; |
Latest revision as of 17:56, 25 July 2024
This page is using the default release RELEASE_SUMO_V1.0_DART-MX8M.
To view this page for a specific Variscite SoM and software release, please follow these steps:
- Visit variwiki.com
- Select your SoM
- Select the software release
In this example we will show how to configure and test SPI1 on DART-MX8M. The SPI pins on external connector J16
are used for SPI loopback test.
Kernel configuration
Verify that the i.MX SPI driver (CONFIG_SPI_IMX) is enabled in your kernel configuration:
- In menuconfig: Device Drivers -> SPI support -> <*> Freescale i.MX SPI controllers
Verify that the User mode SPI driver (CONFIG_SPI_SPIDEV) is enabled in your kernel configuration:
- In menuconfig: Device Drivers -> SPI support -> <*> User mode SPI device driver support
Device Tree configuration
The default DART-MX8M SPI configuration is for resistive touch controller on CS0. For the purpose of loop back test the configuration should be modified to use a different CS line.
Add spidev node
Edit arch/arm64/boot/dts/freescale/fsl-imx8mq-var-dart-common.dtsi to modify cs-gpios property and add spidev node.
GPIO1_12 will be used in this example to control SPI CS0.
&ecspi1 { #address-cells = <1>; #size-cells = <0>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_ecspi1>; cs-gpios = <&gpio1 12 0>; fsl,spi-num-chipselects = <1>; status = "okay"; spidev@0 { compatible = "spidev"; spi-max-frequency = <12000000>; reg = <0>; }; };
Configure SPI1 pins
&iomuxc { imx8m-var-dart { ... pinctrl_ecspi1: ecspi1grp { fsl,pins = < MX8MQ_IOMUXC_ECSPI1_SCLK_ECSPI1_SCLK 0x11 MX8MQ_IOMUXC_ECSPI1_MOSI_ECSPI1_MOSI 0x11 MX8MQ_IOMUXC_ECSPI1_MISO_ECSPI1_MISO 0x11 MX8MQ_IOMUXC_ECSPI1_SS0_GPIO5_IO9 0x11 MX8MQ_IOMUXC_GPIO1_IO12_GPIO1_IO12 0x11 >; }; ... }; };
Recompile the kernel
Compile the kernel (only if kernel configuration was changed) and device tree and update the SOM.
Compile SPI test application
There's an SPI test utility in the kernel source tree: tools/spi/spidev_test.c
To cross compile it, use the following command:
$ $CC ./tools/spi/spidev_test.c -o ./spidev_test
SPI 1 External Connector
SPI 1 will be accessible on the following EVK pins:
- J16.2 - SPI1.SCLK
- J16.4 - SPI1.SS0
- J16.6 - SPI1.MOSI
- J16.8 - SPI1.MISO
Run SPI Test
Copy spidev_test binary to DART-MX8M.
Loop SPI1.MOSI and SPI1.MISO by putting a jumper on J16.6 and J16.8
Configure GPIO5_9 (the default CS0 pin) as output with value 1 to prevent it from interfering with new CS0 pin
# echo 137 > /sys/class/gpio/export # echo out > /sys/class/gpio/gpio137/direction # echo 1 > /sys/class/gpio/gpio137/value
Run SPI test tool
# ./spidev_test -v -D /dev/spidev0.0
The output of successful test should look like this:
spi mode: 0x20 bits per word: 8 max speed: 500000 Hz (500 KHz) TX | FF FF FF FF FF FF 40 00 00 00 00 95 FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF F0 0D | ......@....�..................�. RX | FF FF FF FF FF FF 40 00 00 00 00 95 FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF F0 0D | ......@....�..................�.
Using multiple SPI CS lines
The i.MX8M SPI controllers support up to 4 chip select lines.
In the example below GPIO1_12 and GPIO1_15 are used to control CS0 and CS1 respectively.
When selecting CS GPIO pins make sure they are not used to control other peripherals.
&ecspi1 { #address-cells = <1>; #size-cells = <0>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_ecspi1>; cs-gpios = <&gpio1 12 0>, <&gpio1 15 0>; fsl,spi-num-chipselects = <2>; status = "okay"; chip1@0 { reg = <0>; ... }; chip2@1 { reg = <1>; ... }; };
&iomuxc { imx8m-var-dart { ... pinctrl_ecspi1: ecspi1grp { fsl,pins = < MX8MQ_IOMUXC_ECSPI1_SCLK_ECSPI1_SCLK 0x11 MX8MQ_IOMUXC_ECSPI1_MOSI_ECSPI1_MOSI 0x11 MX8MQ_IOMUXC_ECSPI1_MISO_ECSPI1_MISO 0x11 MX8MQ_IOMUXC_GPIO1_IO12_GPIO1_IO12 0x11 MX8MQ_IOMUXC_GPIO1_I015_GPIO1_IO15 0x11 >; }; ... }; };