DART-MX8M SPI: Difference between revisions
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{{ | <!-- Set release according to "release" parameter in URL and use RELEASE_SUMO_V1.0_DART-MX8M as default | ||
In this example we will show how to configure and test SPI1 on | --> {{INIT_RELEASE_PARAM|RELEASE_SUMO_V1.0_DART-MX8M}}<!-- | ||
--> {{#lst:Yocto_Platform_Customization|{{#var:RELEASE_PARAM}}}} <!-- | |||
--> {{#lst:B2QT_Platform_Customization|{{#var:RELEASE_PARAM}}}} <!-- | |||
--> {{#lst:Android_Platform_Customization|{{#var:RELEASE_PARAM}}}} <!-- | |||
--> {{#lst:Debian_Platform_Customization|{{#var:RELEASE_PARAM}}}} <!-- | |||
--> {{PageHeader|{{#var:HARDWARE_NAME}} SPI}} {{DocImage|category1=Yocto|category2=Android}}[[Category:Debian]][[Category:DART-MX8M]][[Category:DART-MX8M-MINI]][[Category:DART-MX8M-PLUS]]__toc__ | |||
<!-- Set local variables | |||
-->{{#vardefine:DEFAULT_DTS|{{#replace:{{#var:DEFAULT_DTB}}|dtb|dts}}}} | |||
In this example we will show how to configure and test SPI1 on {{#var:HARDWARE_NAME}}. The SPI pins on external connector J16 | |||
are used for SPI loopback test. | are used for SPI loopback test. | ||
Line 13: | Line 22: | ||
= Device Tree configuration = | = Device Tree configuration = | ||
The | {{#switch: {{#var:HARDWARE_NAME}} | ||
For the purpose of loop back test the configuration should be modified to use different CS line. | | VAR-SOM-MX93= | ||
On the {{#var:HARDWARE_NAME}}, lpspi6 is configured with a spidev device that can be used to test SPI. | |||
The following steps demonstrate how to test spidev. | |||
| DART-MX95= | |||
On the {{#var:HARDWARE_NAME}}, lpspi7 is configured with a spidev device that can be used to test SPI. | |||
The following steps demonstrate how to test spidev. | |||
| #default= | |||
The default {{#var:HARDWARE_NAME}} SPI configuration is for resistive touch controller on CS0. | |||
For the purpose of loop back test the configuration should be modified to use a different CS line. | |||
}} | |||
== Add spidev node == | == Add spidev node == | ||
Edit arch/arm64/boot/dts | {{#switch: {{#var:HARDWARE_NAME}} | ||
| DART-MX8M= | |||
Edit {{#ifeq: {{#var:ANDROID_NAME}} | Pie |{{#var:BUILD_FOLDER}}/{{#var:BUILD_FOLDER_ANDROID}}/variscite/kernel_imx/}}arch/arm64/boot/dts/{{#ifeq: {{#var:YOCTO_NAME}} | Morty |variscite/imx8m-var-dart-common.dtsi|freescale/fsl-imx8mq-var-dart-common.dtsi}} to modify cs-gpios property and add spidev node.<br> | |||
GPIO1_12 will be used in this example to control SPI CS0. | |||
<pre> | |||
&ecspi1 { | |||
#address-cells = <1>; | |||
#size-cells = <0>; | |||
pinctrl-names = "default"; | |||
pinctrl-0 = <&pinctrl_ecspi1>; | |||
cs-gpios = <&gpio1 12 0>; | |||
fsl,spi-num-chipselects = <1>; | |||
status = "okay"; | |||
spidev@0 { | |||
compatible = "spidev"; | |||
spi-max-frequency = <12000000>; | |||
reg = <0>; | |||
}; | |||
}; | |||
</pre> | |||
| DART-MX8M-MINI= | |||
Edit {{#ifeq: {{#var:ANDROID_NAME}} | Pie |{{#var:BUILD_FOLDER}}/{{#var:BUILD_FOLDER_ANDROID}}/variscite/kernel_imx/}}/arch/arm64/boot/dts/freescale/{{#var:DEFAULT_DTS}} to modify cs-gpios property and add spidev node.<br> | |||
GPIO1_12 will be used in this example to control SPI CS0. | GPIO1_12 will be used in this example to control SPI CS0. | ||
Line 37: | Line 78: | ||
}; | }; | ||
</pre> | </pre> | ||
| VAR-SOM-MX8M-NANO= | |||
Edit {{#ifeq: {{#var:ANDROID_NAME}} | Pie |{{#var:BUILD_FOLDER}}/{{#var:BUILD_FOLDER_ANDROID}}/variscite/kernel_imx/}}/arch/arm64/boot/dts/freescale/{{#var:DEFAULT_DTS}} to modify cs-gpios property and add spidev node.<br> | |||
GPIO1_0 will be used in this example to control SPI CS0. | |||
<pre> | |||
&ecspi1 { | |||
pinctrl-names = "default"; | |||
pinctrl-0 = <&pinctrl_ecspi1>; | |||
cs-gpios = <&gpio1 0 0>; | |||
fsl,spi-num-chipselects = <1>; | |||
/delete-property/ dmas; | |||
/delete-property/ dma-names; | |||
status = "okay"; | |||
spidev@0 { | |||
compatible = "spidev"; | |||
spi-max-frequency = <12000000>; | |||
reg = <0>; | |||
}; | |||
}; | |||
</pre> | |||
| DART-MX8M-PLUS= | |||
Edit {{#ifeq: {{#var:ANDROID_NAME}} | Pie |{{#var:BUILD_FOLDER}}/{{#var:BUILD_FOLDER_ANDROID}}/variscite/kernel_imx/}}/arch/arm64/boot/dts/freescale/{{#var:DEFAULT_DTS}} to modify cs-gpios property and add spidev node.<br> | |||
GPIO1_12 will be used in this example to control SPI CS0. | |||
<pre> | |||
&ecspi1 { | |||
pinctrl-names = "default"; | |||
pinctrl-0 = <&pinctrl_ecspi1>; | |||
cs-gpios = <&gpio1 12 0>; | |||
status = "okay"; | |||
spidev@0 { | |||
compatible = "spidev"; | |||
spi-max-frequency = <12000000>; | |||
reg = <0>; | |||
}; | |||
}; | |||
</pre> | |||
| VAR-SOM-MX93= | |||
Edit {{#ifeq: {{#var:ANDROID_NAME}} | Pie |{{#var:BUILD_FOLDER}}/{{#var:BUILD_FOLDER_ANDROID}}/variscite/kernel_imx/}}/arch/arm64/boot/dts/freescale/{{#var:DEFAULT_DTS}} to modify cs-gpios property and add spidev node.<br> | |||
GPIO2_0 will be used in this example to control SPI CS0. | |||
<pre> | |||
&lpspi6 { | |||
pinctrl-names = "default"; | |||
pinctrl-0 = <&pinctrl_lpspi6>; | |||
cs-gpios = <&gpio2 0 GPIO_ACTIVE_LOW>; | |||
status = "okay"; | |||
/* Test SPI device */ | |||
spidev@0 { | |||
reg = <0>; | |||
compatible = "var,spidev"; | |||
spi-max-frequency = <1000000>; | |||
status = "okay"; | |||
}; | |||
}; | |||
</pre> | |||
| DART-MX95= | |||
{{#ifeq: {{#var:ANDROID_NAME}} | Pie |{{#var:BUILD_FOLDER}}/{{#var:BUILD_FOLDER_ANDROID}}/variscite/kernel_imx/}}/arch/arm64/boot/dts/freescale/{{#var:DEFAULT_DTS}} provides an enabled spidev node.<br> | |||
GPIO5_4 is used to control SPI CS2 (J25.2 on DT8MCB Carrier) | |||
<pre> | |||
&lpspi7 { | |||
fsl,spi-num-chipselects = <3>; | |||
pinctrl-names = "default", "sleep"; | |||
pinctrl-0 = <&pinctrl_lpspi7>; | |||
pinctrl-1 = <&pinctrl_lpspi7>; | |||
cs-gpios = <&gpio2 14 GPIO_ACTIVE_LOW>, | |||
<&gpio5 13 GPIO_ACTIVE_LOW>, | |||
<&gpio5 4 GPIO_ACTIVE_LOW>; | |||
status = "okay"; | |||
/* Resistive touch controller */ | |||
ads7846@0 { | |||
...... | |||
status = "okay"; | |||
}; | |||
can0: can@1 { | |||
...... | |||
status = "okay"; | |||
}; | |||
spidev0: spi@2 { | |||
reg = <2>; | |||
compatible = "lwn,bk4"; | |||
spi-max-frequency = <1000000>; | |||
}; | |||
}; | |||
</pre> | |||
|}} | |||
== Configure SPI1 pins == | == Configure SPI1 pins == | ||
{{#switch: {{#var:HARDWARE_NAME}} | |||
| DART-MX8M= | |||
<pre> | <pre> | ||
&iomuxc { | &iomuxc { | ||
imx8m-var-dart { | |||
... | ... | ||
pinctrl_ecspi1: ecspi1grp { | |||
fsl,pins = < | fsl,pins = < | ||
MX8MQ_IOMUXC_ECSPI1_SCLK_ECSPI1_SCLK 0x11 | MX8MQ_IOMUXC_ECSPI1_SCLK_ECSPI1_SCLK 0x11 | ||
Line 56: | Line 192: | ||
}; | }; | ||
</pre> | </pre> | ||
| DART-MX8M-MINI= | |||
<pre> | |||
&iomuxc { | |||
imx8mm-var-dart { | |||
... | |||
pinctrl_ecspi1: ecspi1grp { | |||
fsl,pins = < | |||
MX8MM_IOMUXC_ECSPI1_SCLK_ECSPI1_SCLK 0x11 | |||
MX8MM_IOMUXC_ECSPI1_MOSI_ECSPI1_MOSI 0x11 | |||
MX8MM_IOMUXC_ECSPI1_MISO_ECSPI1_MISO 0x11 | |||
MX8MM_IOMUXC_ECSPI1_SS0_GPIO5_IO9 0x11 | |||
MX8MM_IOMUXC_GPIO1_IO12_GPIO1_IO12 0x11 | |||
>; | |||
}; | |||
... | |||
}; | |||
}; | |||
</pre> | |||
| VAR-SOM-MX8M-NANO= | |||
<pre> | |||
&iomuxc { | |||
imx8mn-var-som { | |||
... | |||
pinctrl_ecspi1: ecspi1grp { | |||
fsl,pins = < | |||
MX8MN_IOMUXC_ECSPI1_SCLK_ECSPI1_SCLK 0x13 | |||
MX8MN_IOMUXC_ECSPI1_MOSI_ECSPI1_MOSI 0x13 | |||
MX8MN_IOMUXC_ECSPI1_MISO_ECSPI1_MISO 0x13 | |||
MX8MN_IOMUXC_GPIO1_IO14_GPIO1_IO14 0x13 | |||
MX8MN_IOMUXC_GPIO1_IO00_GPIO1_IO0 0x13 | |||
>; | |||
}; | |||
... | |||
}; | |||
}; | |||
</pre> | |||
| DART-MX8M-PLUS= | |||
<pre> | |||
&iomuxc { | |||
... | |||
pinctrl_ecspi1: ecspi1grp { | |||
fsl,pins = < | |||
MX8MP_IOMUXC_ECSPI1__SCLK_ECSPI1_SCLK 0x11 | |||
MX8MP_IOMUXC_ECSPI1__MOSI_ECSPI1_MOSI 0x11 | |||
MX8MP_IOMUXC_ECSPI1__MISO_ECSPI1_MISO 0x11 | |||
MX8MP_IOMUXC_ECSPI1__SS0_GPIO5_IO9 0x11 | |||
MX8MP_IOMUXC_GPIO1__IO12_GPIO1_IO12 0x11 | |||
>; | |||
}; | |||
... | |||
}; | |||
</pre> | |||
| VAR-SOM-MX93= | |||
<pre> | |||
&iomuxc { | |||
... | |||
pinctrl_lpspi6: lpspi6grp { | |||
fsl,pins = < | |||
MX93_PAD_GPIO_IO00__GPIO2_IO00 0x31e | |||
MX93_PAD_GPIO_IO01__LPSPI6_SIN 0x31e | |||
MX93_PAD_GPIO_IO02__LPSPI6_SOUT 0x31e | |||
MX93_PAD_GPIO_IO03__LPSPI6_SCK 0x31e | |||
>; | |||
}; | |||
... | |||
}; | |||
</pre> | |||
| DART-MX95= | |||
Already configured in the default device tree file | |||
|}} | |||
= Recompile the kernel = | = Recompile the kernel = | ||
Line 62: | Line 268: | ||
= Compile SPI test application = | = Compile SPI test application = | ||
There's an SPI test utility in the kernel source tree: tools/spi/spidev_test.c<br> | There's an SPI test utility in the kernel source tree: tools/spi/spidev_test.c<br> | ||
To cross compile it use the following command | To cross compile it, use the following command: | ||
{{#ifeq: {{#var:ANDROID_NAME}} | Pie | | |||
$ $ | Setup the toolchain path to point to aarch64-linux-android- tools in prebuilts/gcc/linux-x86/aarch64/aarch64-linux-android-4.9/bin | ||
$ export ARCH=arm64 | |||
$ export CROSS_COMPILE={{#var:BUILD_FOLDER}}/{{#var:BUILD_FOLDER_ANDROID}}/prebuilts/gcc/linux-x86/aarch64/aarch64-linux-android-4.9/bin/aarch64-linux-android- | |||
$ cd {{#var:BUILD_FOLDER}}/{{#var:BUILD_FOLDER_ANDROID}}/variscite/kernel_imx/tools/spi/ | |||
$ aarch64-linux-android-gcc spidev_test.c -o ./spidev_test | |||
$ adb root | |||
$ adb remount /system/ | |||
$ adb push spidev_test /system/bin/ | |||
| | |||
$ $CC ./tools/spi/spidev_test.c -o ./spidev_test | |||
}} | |||
== SPI 1 External Connector == | == SPI 1 External Connector == | ||
SPI 1 will be accessible on the following EVK pins: | SPI 1 will be accessible on the following EVK pins: | ||
* J16.2 - SPI1.SCLK | * J16.2 - SPI1.SCLK | ||
{{#switch: {{#var:HARDWARE_NAME}} | |||
| DART-MX95= | |||
* J25.2 - SAI1_RXFS | |||
| #default= | |||
* J16.4 - SPI1.SS0 | * J16.4 - SPI1.SS0 | ||
}} | |||
* J16.6 - SPI1.MOSI | * J16.6 - SPI1.MOSI | ||
* J16.8 - SPI1.MISO | * J16.8 - SPI1.MISO | ||
Line 77: | Line 296: | ||
Copy spidev_test binary to DART-MX8M.<br> | Copy spidev_test binary to DART-MX8M.<br> | ||
Loop SPI1.MOSI and SPI1.MISO by putting a jumper on J16.6 and J16.8<br> | Loop SPI1.MOSI and SPI1.MISO by putting a jumper on J16.6 and J16.8<br> | ||
{{#switch: {{#var:HARDWARE_NAME}} | |||
| VAR-SOM-MX8M-NANO= | |||
Configure GPIO1_14 (the default CS0 pin) as output with value 1 to prevent it from interfering with new CS0 pin | |||
<pre> | |||
# echo 14 > /sys/class/gpio/export | |||
# echo out > /sys/class/gpio/gpio14/direction | |||
# echo 1 > /sys/class/gpio/gpio14/value | |||
</pre> | |||
| VAR-SOM-MX93= | |||
| #default= | |||
Configure GPIO5_9 (the default CS0 pin) as output with value 1 to prevent it from interfering with new CS0 pin | Configure GPIO5_9 (the default CS0 pin) as output with value 1 to prevent it from interfering with new CS0 pin | ||
<pre> | |||
# echo 137 > /sys/class/gpio/export | # echo 137 > /sys/class/gpio/export | ||
# echo out > /sys/class/gpio/gpio137/direction | # echo out > /sys/class/gpio/gpio137/direction | ||
# echo 1 > /sys/class/gpio/gpio137/value | # echo 1 > /sys/class/gpio/gpio137/value | ||
</pre> | |||
}} | |||
Run SPI test tool | Run SPI test tool | ||
{{#ifeq: {{#var:YOCTO_NAME}} | Morty | | |||
<pre> | |||
# ./spidev_test -v -D /dev/spidev32766.0 | |||
</pre> | |||
| | |||
{{#ifeq: {{#var:HARDWARE_NAME}} | DART-MX95 | | |||
<pre> | |||
# ./spidev_test -v -D /dev/spidev0.2 | |||
</pre> | |||
| | |||
<pre> | |||
# ./spidev_test -v -D /dev/spidev0.0 | |||
</pre> | |||
}}}} | |||
The output of successful test should look like this: | The output of successful test should look like this: | ||
Line 96: | Line 340: | ||
= Using multiple SPI CS lines = | = Using multiple SPI CS lines = | ||
The i.MX8M SPI controllers support up to 4 chip select lines.<br> | The {{#switch: {{#var:SOC_FAMILY}} | ||
In the example below GPIO1_12 and GPIO1_15 are used to control CS0 and CS1 respectively.<br> | |imx9=i.MX9 SPI controllers support up to 2 chip select lines. | ||
|imx8m|#default=i.MX8M SPI controllers support up to 4 chip select lines. | |||
}} | |||
<br>In the example below GPIO1_12 and GPIO1_15 are used to control CS0 and CS1 respectively.<br> | |||
When selecting CS GPIO pins make sure they are not used to control other peripherals. | When selecting CS GPIO pins make sure they are not used to control other peripherals. | ||
{{#switch: {{#var:HARDWARE_NAME}} | |||
| VAR-SOM-MX8M-NANO= | |||
<pre> | <pre> | ||
&ecspi1 { | &ecspi1 { | ||
Line 106: | Line 355: | ||
pinctrl-names = "default"; | pinctrl-names = "default"; | ||
pinctrl-0 = <&pinctrl_ecspi1>; | pinctrl-0 = <&pinctrl_ecspi1>; | ||
cs-gpios = <&gpio1 0 0>, | |||
<&gpio1 1 0>; | |||
fsl,spi-num-chipselects = <2>; | |||
status = "okay"; | |||
chip1@0 { | |||
reg = <0>; | |||
... | |||
}; | |||
chip2@1 { | |||
reg = <1>; | |||
... | |||
}; | |||
}; | |||
</pre> | |||
|#VAR-SOM-MX93= | |||
<pre> | |||
&lpspi6 { | |||
pinctrl-names = "default"; | |||
pinctrl-0 = <&pinctrl_lpspi6>; | |||
cs-gpios = <&gpio1 12 0>, | cs-gpios = <&gpio1 12 0>, | ||
<&gpio1 15 0>; | <&gpio1 15 0>; | ||
Line 121: | Line 391: | ||
}; | }; | ||
}; | }; | ||
</pre> | |||
|#default= | |||
<pre> | |||
&ecspi1 { | |||
#address-cells = <1>; | |||
#size-cells = <0>; | |||
pinctrl-names = "default"; | |||
pinctrl-0 = <&pinctrl_ecspi1>; | |||
cs-gpios = <&gpio1 12 0>, | |||
<&gpio1 15 0>; | |||
fsl,spi-num-chipselects = <2>; | |||
status = "okay"; | |||
chip1@0 { | |||
reg = <0>; | |||
... | |||
}; | |||
chip2@1 { | |||
reg = <1>; | |||
... | |||
}; | |||
}; | |||
</pre> | |||
}} | |||
{{#switch: {{#var:HARDWARE_NAME}} | |||
| DART-MX8M= | |||
<pre> | |||
&iomuxc { | &iomuxc { | ||
imx8m-var-dart { | |||
... | ... | ||
pinctrl_ecspi1: ecspi1grp { | |||
fsl,pins = < | fsl,pins = < | ||
MX8MQ_IOMUXC_ECSPI1_SCLK_ECSPI1_SCLK 0x11 | MX8MQ_IOMUXC_ECSPI1_SCLK_ECSPI1_SCLK 0x11 | ||
Line 137: | Line 435: | ||
}; | }; | ||
}; | }; | ||
</pre> | </pre> | ||
| DART-MX8M-MINI= | |||
<pre> | |||
&iomuxc { | |||
imx8mm-var-dart { | |||
... | |||
pinctrl_ecspi1: ecspi1grp { | |||
fsl,pins = < | |||
MX8MM_IOMUXC_ECSPI1_SCLK_ECSPI1_SCLK 0x11 | |||
MX8MM_IOMUXC_ECSPI1_MOSI_ECSPI1_MOSI 0x11 | |||
MX8MM_IOMUXC_ECSPI1_MISO_ECSPI1_MISO 0x11 | |||
MX8MM_IOMUXC_GPIO1_IO12_GPIO1_IO12 0x11 | |||
MX8MM_IOMUXC_GPIO1_I015_GPIO1_IO15 0x11 | |||
>; | |||
}; | |||
... | |||
}; | |||
}; | |||
</pre> | |||
| VAR-SOM-MX8M-MINI= | |||
<pre> | |||
&iomuxc { | |||
imx8mn-var-som { | |||
... | |||
pinctrl_ecspi1: ecspi1grp { | |||
fsl,pins = < | |||
MX8MN_IOMUXC_ECSPI1_SCLK_ECSPI1_SCLK 0x13 | |||
MX8MN_IOMUXC_ECSPI1_MOSI_ECSPI1_MOSI 0x13 | |||
MX8MN_IOMUXC_ECSPI1_MISO_ECSPI1_MISO 0x13 | |||
MX8MN_IOMUXC_GPIO1_IO00_GPIO1_IO0 0x13 | |||
MX8MN_IOMUXC_GPIO1_IO00_GPIO1_IO1 0x13 | |||
>; | |||
}; | |||
... | |||
}; | |||
}; | |||
</pre> | |||
| DART-MX8M-PLUS= | |||
<pre> | |||
&iomuxc { | |||
... | |||
pinctrl_ecspi1: ecspi1grp { | |||
fsl,pins = < | |||
MX8MP_IOMUXC_ECSPI1__SCLK_ECSPI1_SCLK 0x11 | |||
MX8MP_IOMUXC_ECSPI1__MOSI_ECSPI1_MOSI 0x11 | |||
MX8MP_IOMUXC_ECSPI1__MISO_ECSPI1_MISO 0x11 | |||
MX8MP_IOMUXC_GPIO1__IO12_GPIO1_IO12 0x11 | |||
MX8MP_IOMUXC_GPIO1__I015_GPIO1_IO15 0x11 | |||
>; | |||
}; | |||
... | |||
}; | |||
</pre> | |||
}} |
Latest revision as of 17:56, 25 July 2024
This page is using the default release RELEASE_SUMO_V1.0_DART-MX8M.
To view this page for a specific Variscite SoM and software release, please follow these steps:
- Visit variwiki.com
- Select your SoM
- Select the software release
In this example we will show how to configure and test SPI1 on DART-MX8M. The SPI pins on external connector J16
are used for SPI loopback test.
Kernel configuration
Verify that the i.MX SPI driver (CONFIG_SPI_IMX) is enabled in your kernel configuration:
- In menuconfig: Device Drivers -> SPI support -> <*> Freescale i.MX SPI controllers
Verify that the User mode SPI driver (CONFIG_SPI_SPIDEV) is enabled in your kernel configuration:
- In menuconfig: Device Drivers -> SPI support -> <*> User mode SPI device driver support
Device Tree configuration
The default DART-MX8M SPI configuration is for resistive touch controller on CS0. For the purpose of loop back test the configuration should be modified to use a different CS line.
Add spidev node
Edit arch/arm64/boot/dts/freescale/fsl-imx8mq-var-dart-common.dtsi to modify cs-gpios property and add spidev node.
GPIO1_12 will be used in this example to control SPI CS0.
&ecspi1 { #address-cells = <1>; #size-cells = <0>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_ecspi1>; cs-gpios = <&gpio1 12 0>; fsl,spi-num-chipselects = <1>; status = "okay"; spidev@0 { compatible = "spidev"; spi-max-frequency = <12000000>; reg = <0>; }; };
Configure SPI1 pins
&iomuxc { imx8m-var-dart { ... pinctrl_ecspi1: ecspi1grp { fsl,pins = < MX8MQ_IOMUXC_ECSPI1_SCLK_ECSPI1_SCLK 0x11 MX8MQ_IOMUXC_ECSPI1_MOSI_ECSPI1_MOSI 0x11 MX8MQ_IOMUXC_ECSPI1_MISO_ECSPI1_MISO 0x11 MX8MQ_IOMUXC_ECSPI1_SS0_GPIO5_IO9 0x11 MX8MQ_IOMUXC_GPIO1_IO12_GPIO1_IO12 0x11 >; }; ... }; };
Recompile the kernel
Compile the kernel (only if kernel configuration was changed) and device tree and update the SOM.
Compile SPI test application
There's an SPI test utility in the kernel source tree: tools/spi/spidev_test.c
To cross compile it, use the following command:
$ $CC ./tools/spi/spidev_test.c -o ./spidev_test
SPI 1 External Connector
SPI 1 will be accessible on the following EVK pins:
- J16.2 - SPI1.SCLK
- J16.4 - SPI1.SS0
- J16.6 - SPI1.MOSI
- J16.8 - SPI1.MISO
Run SPI Test
Copy spidev_test binary to DART-MX8M.
Loop SPI1.MOSI and SPI1.MISO by putting a jumper on J16.6 and J16.8
Configure GPIO5_9 (the default CS0 pin) as output with value 1 to prevent it from interfering with new CS0 pin
# echo 137 > /sys/class/gpio/export # echo out > /sys/class/gpio/gpio137/direction # echo 1 > /sys/class/gpio/gpio137/value
Run SPI test tool
# ./spidev_test -v -D /dev/spidev0.0
The output of successful test should look like this:
spi mode: 0x20 bits per word: 8 max speed: 500000 Hz (500 KHz) TX | FF FF FF FF FF FF 40 00 00 00 00 95 FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF F0 0D | ......@....�..................�. RX | FF FF FF FF FF FF 40 00 00 00 00 95 FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF F0 0D | ......@....�..................�.
Using multiple SPI CS lines
The i.MX8M SPI controllers support up to 4 chip select lines.
In the example below GPIO1_12 and GPIO1_15 are used to control CS0 and CS1 respectively.
When selecting CS GPIO pins make sure they are not used to control other peripherals.
&ecspi1 { #address-cells = <1>; #size-cells = <0>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_ecspi1>; cs-gpios = <&gpio1 12 0>, <&gpio1 15 0>; fsl,spi-num-chipselects = <2>; status = "okay"; chip1@0 { reg = <0>; ... }; chip2@1 { reg = <1>; ... }; };
&iomuxc { imx8m-var-dart { ... pinctrl_ecspi1: ecspi1grp { fsl,pins = < MX8MQ_IOMUXC_ECSPI1_SCLK_ECSPI1_SCLK 0x11 MX8MQ_IOMUXC_ECSPI1_MOSI_ECSPI1_MOSI 0x11 MX8MQ_IOMUXC_ECSPI1_MISO_ECSPI1_MISO 0x11 MX8MQ_IOMUXC_GPIO1_IO12_GPIO1_IO12 0x11 MX8MQ_IOMUXC_GPIO1_I015_GPIO1_IO15 0x11 >; }; ... }; };