DART-6UL UART: Difference between revisions

From Variscite Wiki
(Created page with "{{PageHeader|DART-6UL - External UART}} {{DocImage|category1=DART-6UL|category2=Yocto}} __toc__ = Test = By default, Variscite configured UART1, ttymxc2. to test:<br> <br/>Use...")
 
Line 10: Line 10:




Edit arch/arm/boot/dts/imx6qdl-var-som.dtsi
Edit arch/arm/boot/dts/imx6ull-var-dart.dts
Look for:
Look for:
<pre>
<pre>
/* ttymxc2 UART */
/* ttymxc2 UART */
&uart3 {
&uart3 {
                pinctrl-names = "default";
pinctrl-names = "default";
                pinctrl-0 = <&pinctrl_uart3_2>;
pinctrl-0 = <&pinctrl_uart3>;
                fsl,uart-has-rtscts;
fsl,uart-has-rtscts;
                status = "okay";
status = "okay";
};
};
</pre>
</pre>
Line 26: Line 26:
<pre>
<pre>
&uart4 {
&uart4 {
                pinctrl-names = "default";
pinctrl-names = "default";
                pinctrl-0 = <&pinctrl_uart4_1>;
pinctrl-0 = <&pinctrl_uart4>;
                fsl,uart-has-rtscts;
fsl,uart-has-rtscts;
                status = "okay";
status = "okay";
};
};
</pre>
</pre>
Line 35: Line 35:
Duplicate the corresponding pinctrl. Copy :
Duplicate the corresponding pinctrl. Copy :
<pre>
<pre>
                                /* Variscite Uart3 support */
pinctrl_uart2: uart2grp {
                                pinctrl_uart3_2: uart3grp-2 {       /* RX/TX RTS/CTS */
fsl,pins = <
                                                fsl,pins = <
MX6UL_PAD_UART2_TX_DATA__UART2_DCE_TX 0x1b0b1
                                                                MX6QDL_PAD_EIM_D25__UART3_RX_DATA    0x1b0b1
MX6UL_PAD_UART2_RX_DATA__UART2_DCE_RX 0x1b0b1
                                                                MX6QDL_PAD_EIM_D24__UART3_TX_DATA    0x1b0b1
MX6UL_PAD_UART2_CTS_B__UART2_DCE_CTS 0x1b0b1
                                                                MX6QDL_PAD_EIM_D23__UART3_CTS_B      0x1b0b1
MX6UL_PAD_UART2_RTS_B__UART2_DCE_RTS 0x1b0b1
                                                                MX6QDL_PAD_EIM_EB3__UART3_RTS_B      0x1b0b1
>;
                                                >;
};
                                };
</pre>
</pre>
Into:
Into:
<pre>
<pre>
                                /* Variscite Uart4 support */
pinctrl_uart4: uart4grp {
                                pinctrl_uart4_1: uart4grp-1 {       /* RX/TX RTS/CTS */
fsl,pins = <
                                                fsl,pins = <
                                MX6UL_PAD_UART4_TX_DATA__UART3_DCE_TX  0x1b0b1
                                                                MX6QDL_PAD_KEY_COL0__UART4_RX_DATA    0x1b0b1
                                MX6UL_PAD_UART4_RX_DATA__UART4_DCE_RX  0x1b0b1
                                                                MX6QDL_PAD_KEY_COL0__UART4_TX_DATA    0x1b0b1
MX6UL_PAD_ENET1_RX_DATA1__UART4_DCE_CTS 0x1b0b1
                                                                MX6QDL_PAD_CSI0_DAT16__UART4_RTS_B    0x1b0b1
MX6UL_PAD_ENET1_RX_DATA0__UART4_DCE_RTS 0x1b0b1
                                                                MX6QDL_PAD_CSI0_DAT16__UART4_CTS_B    0x1b0b1
>;
                                                >;
};
</pre>                               };
</pre>
The pins are set arbitrary. You should set them based on your hardware design.
The pins are set arbitrary. You should set them based on your hardware design.

Revision as of 08:10, 28 December 2015

DART-6UL - External UART

Test

By default, Variscite configured UART1, ttymxc2. to test:

Use minicom to connect.
Set the serial to ttymxc2
You can use a loopback or connect to anther computer

Example: configure UART4, ttymxc3

Edit arch/arm/boot/dts/imx6ull-var-dart.dts Look for:

/* ttymxc2 UART */
&uart3 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_uart3>;
	fsl,uart-has-rtscts;
	status = "okay";
};

Duplicate it and change the name and the pinctrl name. For Example:

&uart4 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_uart4>;
	fsl,uart-has-rtscts;
	status = "okay";
};

Duplicate the corresponding pinctrl. Copy :

		pinctrl_uart2: uart2grp {
			fsl,pins = <
				MX6UL_PAD_UART2_TX_DATA__UART2_DCE_TX	0x1b0b1
				MX6UL_PAD_UART2_RX_DATA__UART2_DCE_RX	0x1b0b1
				MX6UL_PAD_UART2_CTS_B__UART2_DCE_CTS	0x1b0b1
				MX6UL_PAD_UART2_RTS_B__UART2_DCE_RTS	0x1b0b1
			>;
		};

Into:

		pinctrl_uart4: uart4grp {
			fsl,pins = <
                                MX6UL_PAD_UART4_TX_DATA__UART3_DCE_TX   0x1b0b1
                                MX6UL_PAD_UART4_RX_DATA__UART4_DCE_RX   0x1b0b1
				MX6UL_PAD_ENET1_RX_DATA1__UART4_DCE_CTS	0x1b0b1
				MX6UL_PAD_ENET1_RX_DATA0__UART4_DCE_RTS	0x1b0b1
			>;
		};

The pins are set arbitrary. You should set them based on your hardware design.