VAR-SOM-MX6 UART: Difference between revisions
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= Add additional UART = | = Add additional UART = | ||
Edit arch/arm/boot/dts/imx6qdl-var-som.dtsi | |||
Look for: | |||
<pre> | |||
/* ttymxc2 UART */ | |||
&uart3 { | |||
pinctrl-names = "default"; | |||
pinctrl-0 = <&pinctrl_uart3_2>; | |||
fsl,uart-has-rtscts; | |||
status = "okay"; | |||
}; | |||
</pre> | |||
Duplicate it and change the name and the pinctrl name. | |||
For Example: | |||
<pre> | |||
&uart4 { | |||
pinctrl-names = "default"; | |||
pinctrl-0 = <&pinctrl_uart4_1>; | |||
fsl,uart-has-rtscts; | |||
status = "okay"; | |||
}; | |||
</pre> | |||
Now duplicate the pinctrl copy : | |||
<pre> | |||
/* Variscite Uart2 support */ | |||
pinctrl_uart3_2: uart3grp-2 { /* RX/TX RTS/CTS */ | |||
fsl,pins = < | |||
MX6QDL_PAD_EIM_D25__UART3_RX_DATA 0x1b0b1 | |||
MX6QDL_PAD_EIM_D24__UART3_TX_DATA 0x1b0b1 | |||
MX6QDL_PAD_EIM_D23__UART3_CTS_B 0x1b0b1 | |||
MX6QDL_PAD_EIM_EB3__UART3_RTS_B 0x1b0b1 | |||
>; | |||
}; | |||
</pre> | |||
Into: | |||
<pre> | |||
/* Variscite Uart3 support */ | |||
pinctrl_uart4_1: uart4grp-1 { /* RX/TX RTS/CTS */ | |||
fsl,pins = < | |||
MX6QDL_PAD_KEY_COL0__UART4_RX_DATA 0x1b0b1 | |||
MX6QDL_PAD_KEY_COL0__UART4_TX_DATA 0x1b0b1 | |||
MX6QDL_PAD_CSI0_DAT16__UART4_RTS_B 0x1b0b1 | |||
MX6QDL_PAD_CSI0_DAT16__UART4_CTS_B 0x1b0b1 | |||
>; | |||
</pre> }; | |||
The pins are set arbitrary. You should set them based on your hardware design. |
Revision as of 10:04, 15 December 2015
VAR-SOM-MX6 - External UART
Test
Use minicom to connect.
Set the serial to ttymxc2
You can use a loopback or connect to anther computer
Add additional UART
Edit arch/arm/boot/dts/imx6qdl-var-som.dtsi Look for:
/* ttymxc2 UART */ &uart3 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart3_2>; fsl,uart-has-rtscts; status = "okay"; };
Duplicate it and change the name and the pinctrl name. For Example:
&uart4 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart4_1>; fsl,uart-has-rtscts; status = "okay"; };
Now duplicate the pinctrl copy :
/* Variscite Uart2 support */ pinctrl_uart3_2: uart3grp-2 { /* RX/TX RTS/CTS */ fsl,pins = < MX6QDL_PAD_EIM_D25__UART3_RX_DATA 0x1b0b1 MX6QDL_PAD_EIM_D24__UART3_TX_DATA 0x1b0b1 MX6QDL_PAD_EIM_D23__UART3_CTS_B 0x1b0b1 MX6QDL_PAD_EIM_EB3__UART3_RTS_B 0x1b0b1 >; };
Into:
/* Variscite Uart3 support */ pinctrl_uart4_1: uart4grp-1 { /* RX/TX RTS/CTS */ fsl,pins = < MX6QDL_PAD_KEY_COL0__UART4_RX_DATA 0x1b0b1 MX6QDL_PAD_KEY_COL0__UART4_TX_DATA 0x1b0b1 MX6QDL_PAD_CSI0_DAT16__UART4_RTS_B 0x1b0b1 MX6QDL_PAD_CSI0_DAT16__UART4_CTS_B 0x1b0b1 >;
};
The pins are set arbitrary. You should set them based on your hardware design.