Zephyr Platform Customization: Difference between revisions
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== Releases == | == Releases == | ||
=== zephyr-mx8mp-v1.0 === | === zephyr-4.0.0-mx8mp-v1.0 === | ||
<section begin= | <section begin=ZEPHYR_4.0.0_V1.0_DART-MX8M-PLUS/><!-- | ||
-->{{#vardefine:OS|Zephyr}}<!-- | -->{{#vardefine:OS|Zephyr}}<!-- | ||
-->{{#vardefine:HARDWARE_NAME|DART-MX8M-PLUS}}<!-- | -->{{#vardefine:HARDWARE_NAME|DART-MX8M-PLUS}}<!-- | ||
-->{{#vardefine:HARDWARE_NAME1|VAR-SOM-MX8M-PLUS}}<!-- | -->{{#vardefine:HARDWARE_NAME1|VAR-SOM-MX8M-PLUS}}<!-- | ||
-->{{#vardefine:RELEASE_NAME|zephyr-mx8mp-v1.0}}<!-- | -->{{#vardefine:RELEASE_NAME|zephyr-4.0.0-mx8mp-v1.0}}<!-- | ||
-->{{#vardefine:RELEASE_LINK| | -->{{#vardefine:RELEASE_LINK|ZEPHYR_4.0.0_V1.0_DART-MX8M-PLUS}}<!-- | ||
-->{{#vardefine:SDK_PATH|~/zephyrproject/zephyr}}<!-- | -->{{#vardefine:SDK_PATH|~/zephyrproject/zephyr}}<!-- | ||
-->{{#vardefine:SDK_GIT_URL|https://github.com/ | -->{{#vardefine:SDK_GIT_URL|https://github.com/varigit/zephyr}}<!-- | ||
-->{{#vardefine:SDK_GIT_BRANCH| | -->{{#vardefine:SDK_GIT_BRANCH|v4.0-branch_var01}}<!-- | ||
-->{{#vardefine:ZEPHYR_VERSION| | -->{{#vardefine:ZEPHYR_VERSION|4.0.0}}<!-- | ||
-->{{#vardefine:BOARD_FOLDER|boards/variscite/imx8mp_var}}<!-- | -->{{#vardefine:BOARD_FOLDER|boards/variscite/imx8mp_var}}<!-- | ||
-->{{#vardefine:DOCS_FOLDER|doc}}<!-- | -->{{#vardefine:DOCS_FOLDER|doc}}<!-- | ||
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-->{{#vardefine:CORTEX_A_TYPE|a53}}<!-- | -->{{#vardefine:CORTEX_A_TYPE|a53}}<!-- | ||
--><section end= | --><section end=ZEPHYR_4.0.0_V1.0_DART-MX8M-PLUS/><!-- | ||
-->*HARDWARE_NAME = '''{{#var:HARDWARE_NAME}}''' | -->*HARDWARE_NAME = '''{{#var:HARDWARE_NAME}}''' | ||
*RELEASE_NAME = '''{{#var:RELEASE_NAME}}''' | *RELEASE_NAME = '''{{#var:RELEASE_NAME}}''' | ||
Revision as of 15:04, 17 February 2025
DART-MX8M-PLUS
Sections
Available dtbs
To allow Cortex M7 accessing shared resources without experiencing Linux kernel conflicts, a dedicated device tree must be loaded, containing m7 label in the name, using the fdt_file environment variable in U-Boot.
This device tree disables some of the base device tree nodes in order to avoid conflicts between the main processor and Cortex M7.
| File Name |
Description |
|---|---|
| imx8mp-var-dart-dt8mcustomboard-m7.dtb | DART-MX8M-PLUS device tree blob for kernel >= 5.4.70 (Yocto Zeus) on DT8MCustomBoard 2.x |
| imx8mp-var-dart-dt8mcustomboard-legacy-m7.dtb | DART-MX8M-PLUS device tree blob for kernel >= 5.4.70 (Yocto Zeus) on on DT8MCustomBoard 1.x |
| imx8mp-var-som-symphony-m7.dtb | VAR-SOM-MX8M-PLUS device tree blob for kernels >= 5.4.70 (Yocto Zeus) on on Symphony-Board |
| imx8mp-var-som-symphony-2nd-ov5640m7.dtb | VAR-SOM-MX8M-PLUS device tree blob for kernels >= 5.4.70 (Yocto Zeus) on on Symphony-Board with 2nd OV5640 |
Default pins
Default pins used by the demos are:
| DART-MX8M-PLUS | ||||
|---|---|---|---|---|
| Function | SoC balls | SoM pins | DT8MCB pins | Notes |
| UART3 RX/TX | AE6 / AJ4 | J2.87 / J2.89 | J12.11 / J12.13 | Zephyr debug console |
| GPIO3_IO09 | N24 | J1.46 | J41.3 | Output of the Blinky/Button demo Pin referenced to 1.8V |
| GPIO3_IO08 | L24 | J1.50 | J41.5 | Input of the Button demo Pin referenced to 1.8V |
| VAR-SOM-MX8M-PLUS | ||||
|---|---|---|---|---|
| Function | SoC balls | SoM pins | Symphony pins | Notes |
| UART4 RX/TX | AH5 / AJ5 | J1.115 / J1.171 | J18.9 / J18.7 | Zephyr debug console |
| GPIO3_IO14 | R26 | J1.79 | J17.10 | Output of the Blinky/Button demo Pin referenced to 1.8V |
| GPIO3_IO06 | R25 | J1.84 | J17.3 | Input of the Button demo Pin referenced to 1.8V |
Available Demos
- samples/hello_world
- samples/basic/blinky
- samples/basic/button
JTAG
The VAR-SOM-MX8M-PLUS exposes JTAG interface via an optional 10-pin header, on the SOM top left side.
The DART-MX8M-PLUS exports JTAG interface via an optional 10-pin header, on the DT8MCustomBoard top side.
Here is the pinout:
| pin | signal | description | pin | signal | description |
|---|---|---|---|---|---|
| 1 | JTAG_VREF | JTAG IO reference voltage, connected to SOM_3V3_PER via 150 Ohm. |
2 | JTAG_TMS | JTAG Mode Select signal |
| 3 | GND | Digital Ground | 4 | JTAG_TCK | JTAG Clock signal, include PD of 8.2K Ohm. |
| 5 | GND | Digital Ground | 6 | JTAG_TDO | JTAG Data Out signal |
| 7 | GND | Digital Ground | 8 | JTAG_TDI | JTAG Data In signal |
| 9 | JTAG_TRST_B | JTAG Reset signal, active low signal |
10 | POR_B | Programmer Reset, used to put the SOC in reset state. |
Please refer to SoM datasheet for further details.
Releases
zephyr-4.0.0-mx8mp-v1.0
*HARDWARE_NAME = DART-MX8M-PLUS
- RELEASE_NAME = zephyr-4.0.0-mx8mp-v1.0
- RELEASE_LINK = ZEPHYR_4.0.0_V1.0_DART-MX8M-PLUS
- SDK_PATH = ~/zephyrproject/zephyr
- SDK_GIT_URL = https://github.com/varigit/zephyr
- SDK_GIT_BRANCH = v4.0-branch_var01
- ZEPHYR_VERSION = 4.0.0
- BOARD_FOLDER = boards/variscite/imx8mp_var
- DOCS_FOLDER = doc
- PINS_SECTION = DART-MX8M-PLUS_PINS_SECTION
- DEMOS_SECTION = DART-MX8M-PLUS_DEMOS_SECTION
- DTBS_SECTION = DART-MX8M-PLUS_DTBS_SECTION
- JTAG_SECTION = DART-MX8M-PLUS_JTAG_SECTION
- NXP_REFERENCE_KIT = EVK-MIMX8MP
- YOCTO_RELEASE_TAG = mx8mp-yocto-scarthgap-6.6.23_2.0.0-v1.1