MPC VAR-SOM-MX93: Difference between revisions

@@ Line 36: / Line 36: @@
 <includeonly><section begin=RN_MCUXPRESSO_2.13.1_V1.0_VAR-SOM-MX93/>
 |-
 | <span {{#var:STYLE_RELEASE}}>Release 1.0</span> ||
 |-
 | Initial release || First release for the Cortex-M33 core on the VAR-SOM-MX93.
-|
 |-
-| '''Tests conducted on:'''
+| Introduce EEPROM v2 Structure || Changes to SOM EEPROM format for SOM DDR init purposes
 |-
-| GPIO/LED
+| Support for multiple RAM parts and sizes using the EEPROM ||
 |-
-| I2C3/I2C4
+| Support for multiple DDR frequency setpoints ||
 |-
-| ECSPI1/ECSPI2
+| Additional remoteproc M33 demo packaged || hello_world example in freertos-variscite
 |-
-| PWM3/PWM2
+| '''Known Issues'''
 |-
-| UART3/UART4
+| Several features still not yet supported by the NXP BSP: ||
-|-
+- CPU frequency scaling (See L6.1.1_1.0.1_LINUX_RN Table 8)<br>
-| RPMSG
+- Encrypted FS<br>
 |-
 <section end=RN_MCUXPRESSO_2.13.1_V1.0_VAR-SOM-MX93/></includeonly>

Revision as of 14:38, 4 August 2023