Template:GPIO KERNEL UBOOT DRAFT: Difference between revisions

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--> {{#lst:Yocto_Platform_Customization|{{#var:RELEASE_PARAM|RELEASE_SUMO_V1.0_VAR-SOM-MX8X}}}} <!--
--> {{PageHeader|{{#var:HARDWARE_NAME}} GPIO}} {{DocImage|category1=Yocto|category2={{#var:HARDWARE_NAME}}}} __toc__
= Kernel Device Tree GPIO configuration =
= Kernel Device Tree GPIO configuration =
== Device Tree GPIO files ==
== Device Tree GPIO files ==
=== Pin Func files ===
=== Pin Func files ===
{{#ifeq: {{#var:HARDWARE_NAME}} | VAR-SOM-MX8X |
{{#switch: {{#var:HARDWARE_NAME}} | VAR-SOM-MX8=
In the directory include/dt-bindings/pinctrl/ of the Linux kernel source you will find the pin functions definition files.<br>
The relevant file is pads-imx8qm.h.<br>
If you search it for GPIO2_IO07, for example, you will see a group of definitions with same prefix (pad name), "SC_P_ESAI1_SCKT".
<pre>
#define SC_P_ESAI1_SCKT_AUD_ESAI1_SCKT                          SC_P_ESAI1_SCKT                    0
#define SC_P_ESAI1_SCKT_AUD_SAI2_RXC                            SC_P_ESAI1_SCKT                    1
#define SC_P_ESAI1_SCKT_AUD_SPDIF0_EXT_CLK                      SC_P_ESAI1_SCKT                    2
#define SC_P_ESAI1_SCKT_LSIO_GPIO2_IO07                        SC_P_ESAI1_SCKT                    3
</pre>
 
| DART-MX8M=
In the directory {{#ifeq: {{#var:ANDROID_NAME}} | Pie |{{#var:BUILD_FOLDER}}/{{#var:BUILD_FOLDER_ANDROID}}/variscite/kernel_imx/}}arch/arm64/boot/dts/freescale of the Linux kernel source you will find the pin functions definition files.<br>
The relevant file is imx8mq-pinfunc.h.<br>
If you search it for GPIO4_IO2, for example, you will see a group of definitions with same prefix (pad name), "MX8MQ_IOMUXC_SAI1_RXD0".
<pre>
#define MX8MQ_IOMUXC_SAI1_RXD0_SAI1_RX_DATA0                                0x164 0x3CC 0x000 0x0 0x0
#define MX8MQ_IOMUXC_SAI1_RXD0_SAI5_RX_DATA0                                0x164 0x3CC 0x4D4 0x1 0x1
#define MX8MQ_IOMUXC_SAI1_RXD0_CORESIGHT_TRACE0                            0x164 0x3CC 0x000 0x4 0x0
#define MX8MQ_IOMUXC_SAI1_RXD0_GPIO4_IO2                                    0x164 0x3CC 0x000 0x5 0x0
#define MX8MQ_IOMUXC_SAI1_RXD0_CCMSRCGPCMIX_BOOT_CFG0                      0x164 0x3CC 0x000 0x6 0x0
#define MX8MQ_IOMUXC_SAI1_RXD0_SIM_M_HADDR17                                0x164 0x3CC 0x000 0x7 0x0
</pre>
 
| DART-MX8M-MINI=
In the directory {{#ifeq: {{#var:ANDROID_NAME}} | Pie |{{#var:BUILD_FOLDER}}/{{#var:BUILD_FOLDER_ANDROID}}/variscite/kernel_imx/}}arch/arm64/boot/dts/freescale of the Linux kernel source you will find the pin functions definition files.<br>
The relevant file is imx8mm-pinfunc.h.<br>
If you search it for GPIO4_IO2, for example, you will see a group of definitions with same prefix (pad name), "MX8MM_IOMUXC_SAI1_RXD0".
<pre>
#define MX8MM_IOMUXC_SAI1_RXD0_SAI1_RX_DATA0                                0x164 0x3CC 0x000 0x0 0x0
#define MX8MM_IOMUXC_SAI1_RXD0_SAI5_RX_DATA0                                0x164 0x3CC 0x4D4 0x1 0x1
#define MX8MM_IOMUXC_SAI1_RXD0_PDM_DATA0                                    0x164 0x3CC 0x534 0x3 0x1
#define MX8MM_IOMUXC_SAI1_RXD0_CORESIGHT_TRACE0                            0x164 0x3CC 0x000 0x4 0x0
#define MX8MM_IOMUXC_SAI1_RXD0_GPIO4_IO2                                    0x164 0x3CC 0x000 0x5 0x0
#define MX8MM_IOMUXC_SAI1_RXD0_CCMSRCGPCMIX_BOOT_CFG0                      0x164 0x3CC 0x000 0x6 0x0
#define MX8MM_IOMUXC_SAI1_RXD0_SIM_M_HADDR17                                0x164 0x3CC 0x000 0x7 0x0
</pre>
 
| VAR-SOM-MX8M-NANO=
In the directory {{#ifeq: {{#var:ANDROID_NAME}} | Pie |{{#var:BUILD_FOLDER}}/{{#var:BUILD_FOLDER_ANDROID}}/variscite/kernel_imx/}}arch/arm64/boot/dts/freescale of the Linux kernel source you will find the pin functions definition files.<br>
The relevant file is imx8mn-pinfunc.h.<br>
If you search it for GPIO4_IO22, for example, you will see a group of definitions with same prefix (pad name), "MX8MN_IOMUXC_SAI2_RXC".
<pre>
#define MX8MN_IOMUXC_SAI2_RXC_SAI2_RX_BCLK                                  0x01B4 0x041C 0x0000 0x0 0x0
#define MX8MN_IOMUXC_SAI2_RXC_SAI5_TX_BCLK                                  0x01B4 0x041C 0x04E8 0x1 0x2
#define MX8MN_IOMUXC_SAI2_RXC_UART1_DCE_RX                                  0x01B4 0x041C 0x04F4 0x4 0x3
#define MX8MN_IOMUXC_SAI2_RXC_UART1_DTE_TX                                  0x01B4 0x041C 0x0000 0x4 0x0
#define MX8MN_IOMUXC_SAI2_RXC_GPIO4_IO22                                    0x01B4 0x041C 0x0000 0x5 0x0
#define MX8MN_IOMUXC_SAI2_RXC_PDM_BIT_STREAM1                              0x01B4 0x041C 0x0538 0x6 0x8
</pre>
 
| DART-MX8M-PLUS=
In the directory {{#ifeq: {{#var:ANDROID_NAME}} | Pie |{{#var:BUILD_FOLDER}}/{{#var:BUILD_FOLDER_ANDROID}}/variscite/kernel_imx/}}arch/arm64/boot/dts/freescale of the Linux kernel source you will find the pin functions definition files.<br>
The relevant file is imx8mp-pinfunc.h.<br>
If you search it for GPIO4_IO22, for example, you will see a group of definitions with same prefix (pad name), "MX8MP_IOMUXC_SAI2_RXC".
<pre>
#define MX8MP_IOMUXC_SAI2_RXC__AUDIOMIX_SAI2_RX_BCLK                0x1A0 0x400 0x000 0x0 0x0
#define MX8MP_IOMUXC_SAI2_RXC__AUDIOMIX_SAI5_TX_BCLK                0x1A0 0x400 0x50C 0x1 0x2
#define MX8MP_IOMUXC_SAI2_RXC__CAN1_TX                              0x1A0 0x400 0x000 0x3 0x0
#define MX8MP_IOMUXC_SAI2_RXC__UART1_DCE_RX                          0x1A0 0x400 0x5E8 0x4 0x3
#define MX8MP_IOMUXC_SAI2_RXC__UART1_DTE_TX                          0x1A0 0x400 0x000 0x4 0x0
#define MX8MP_IOMUXC_SAI2_RXC__GPIO4_IO22                            0x1A0 0x400 0x000 0x5 0x0
#define MX8MP_IOMUXC_SAI2_RXC__AUDIOMIX_PDM_BIT_STREAM01            0x1A0 0x400 0x4C4 0x6 0x5
 
</pre>
| VAR-SOM-MX93=
In the directory arch/arm64/boot/dts/freescale of the Linux kernel source you will find the pin functions definition files.<br>
The relevant file is imx93-pinfunc.h.<br>
If you search it for GPIO_IO25, for example, you will see a group of definitions with same prefix (pad name), "MX93_PAD_GPIO_IO25".
<pre>
#define MX93_PAD_GPIO_IO25__GPIO2_IO25                            0x0074 0x0224 0x0000 0x0 0x0
#define MX93_PAD_GPIO_IO25__USDHC3_DATA1                          0x0074 0x0224 0x0464 0x1 0x0
#define MX93_PAD_GPIO_IO25__CAN2_TX                              0x0074 0x0224 0x0000 0x2 0x0
#define MX93_PAD_GPIO_IO25__MEDIAMIX_DISP_DATA21                  0x0074 0x0224 0x0000 0x3 0x0
#define MX93_PAD_GPIO_IO25__TPM4_CH3                              0x0074 0x0224 0x0000 0x4 0x0
#define MX93_PAD_GPIO_IO25__JTAG_MUX_TCK                          0x0074 0x0224 0x03D4 0x5 0x1
#define MX93_PAD_GPIO_IO25__LPSPI7_PCS1                          0x0074 0x0224 0x0000 0x6 0x0
#define MX93_PAD_GPIO_IO25__FLEXIO1_FLEXIO25                      0x0074 0x0224 0x03C4 0x7 0x0
</pre>
 
| VAR-SOM-MX8X=
In the directory include/dt-bindings/pinctrl/ of the Linux kernel source you will find the pin functions definition files.<br>
In the directory include/dt-bindings/pinctrl/ of the Linux kernel source you will find the pin functions definition files.<br>
The relevant file is pads-imx8qxp.h.<br>
The relevant file is pads-imx8qxp.h.<br>
Line 18: Line 93:
#define SC_P_MCLK_OUT0_LSIO_GPIO0_IO20                          SC_P_MCLK_OUT0                    4
#define SC_P_MCLK_OUT0_LSIO_GPIO0_IO20                          SC_P_MCLK_OUT0                    4
</pre>
</pre>
}}


Adding only the one with the GPIO0_IO20 suffix (function) to your DTS file will let you use the pin as GPIO.
Adding only the one with the {{#switch: {{#var:HARDWARE_NAME}}|VAR-SOM-MX8=GPIO2_IO07|VAR-SOM-MX93=GPIO2_IO25|VAR-SOM-MX8X=GPIO0_IO20|GPIO4_IO2}} suffix (function) to your dts file will let you use the pin as GPIO.


|
== Define a pin as GPIO in the kernel Device Tree ==
In the directory include/dt-bindings/pinctrl/ of the Linux kernel source you will find the pin functions definition files.<br>
You need to add the relevant definitions to your device tree, as explained in the [[#Pin Func files|Pin Func files]] section above.<br>
The relevant file is pads-imx8qm.h.<br>
{{#switch: {{#var:HARDWARE_NAME}} | VAR-SOM-MX8=
If you search it for GPIO2_IO07, for example, you will see a group of definitions with same prefix (pad name), "SC_P_ESAI1_SCKT".
Edit arch/arm64/boot/dts/freescale/fsl-imx8qm-var-som.dts and add the definition for the GPIO you need in the iomuxc node.<br>
<pre>
&iomuxc {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_hog>;
 
imx8qm-var-som {
pinctrl_hog: hoggrp {
fsl,pins = <
/* Add your GPIO definitions here */
>;
};
};
...
};
</pre>
 
| DART-MX8M=
Edit {{#ifeq: {{#var:ANDROID_NAME}} | Pie |{{#var:BUILD_FOLDER}}/{{#var:BUILD_FOLDER_ANDROID}}/variscite/kernel_imx/}}arch/arm64/boot/dts/{{#ifeq: {{#var:YOCTO_NAME}} | Morty |variscite/imx8m-var-dart-common.dtsi|freescale/{{#var:DTB_PREFIX|fsl-imx8mq-var-dart}}{{#ifeq: {{#sub:{{#var:KERNEL_VER}}|0|2}} | 4. | -common | }}.dtsi}} and add the definition for the GPIO you need in the iomuxc node.<br>
<pre>
<pre>
#define SC_P_ESAI1_SCKT_AUD_ESAI1_SCKT                          SC_P_ESAI1_SCKT                    0
&iomuxc {
#define SC_P_ESAI1_SCKT_AUD_SAI2_RXC                            SC_P_ESAI1_SCKT                    1
pinctrl-names = "default";
#define SC_P_ESAI1_SCKT_AUD_SPDIF0_EXT_CLK                      SC_P_ESAI1_SCKT                    2
pinctrl-0 = <&pinctrl_hog>;
#define SC_P_ESAI1_SCKT_LSIO_GPIO2_IO07                        SC_P_ESAI1_SCKT                    3
 
imx8m-var-dart {
pinctrl_hog: hoggrp {
fsl,pins = <
/* Add your GPIO definitions here */
>;
};
};
…
};
</pre>
</pre>


Adding only the one with the GPIO2_IO07 suffix (function) to your DTS file will let you use the pin as GPIO.
| DART-MX8M-MINI=
}}
Edit {{#ifeq: {{#var:ANDROID_NAME}} | Pie |{{#var:BUILD_FOLDER}}/{{#var:BUILD_FOLDER_ANDROID}}/variscite/kernel_imx/}}arch/arm64/boot/dts/freescale/{{#var:DTB_PREFIX|fsl-imx8mm-var-dart}}.dts and add the definition for the GPIO you need in the iomuxc node.<br>
<pre>
&iomuxc {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_hog>;


imx8mm-var-dart {
pinctrl_hog: hoggrp {
fsl,pins = <
/* Add your GPIO definitions here */
>;
};
};
…
};
</pre>


== Define a pin as GPIO in the kernel Device Tree ==
| VAR-SOM-MX8M-NANO=
You need to add the relevant definitions to your device tree, as explained in the [[#Pin Func files|Pin Func files]] section above.<br>
Edit {{#ifeq: {{#var:ANDROID_NAME}} | Pie |{{#var:BUILD_FOLDER}}/{{#var:BUILD_FOLDER_ANDROID}}/variscite/kernel_imx/}}arch/arm64/boot/dts/freescale/{{#var:DTB_PREFIX|fsl-imx8mn-var-som}}.dts and add the definition for the GPIO you need in the iomuxc node.<br>
{{#ifeq: {{#var:HARDWARE_NAME}} | VAR-SOM-MX8X |
Edit arch/arm64/boot/dts/freescale/fsl-imx8qxp-var-som-common.dtsi and add the definition for the GPIO you need in the iomuxc node.<br>
<pre>
<pre>
&iomuxc {
&iomuxc {
Line 45: Line 160:
pinctrl-0 = <&pinctrl_hog>;
pinctrl-0 = <&pinctrl_hog>;


imx8qxp-var-som {
imx8mn-var-som {
pinctrl_hog: hoggrp {
pinctrl_hog: hoggrp {
fsl,pins = <
fsl,pins = <
Line 52: Line 167:
};
};
};
};
...
…
};
</pre>
 
| DART-MX8M-PLUS=
Edit {{#ifeq: {{#var:ANDROID_NAME}} | Pie |{{#var:BUILD_FOLDER}}/{{#var:BUILD_FOLDER_ANDROID}}/variscite/kernel_imx/}}arch/arm64/boot/dts/freescale/imx8mp-var-dart.dts and add the definition for the GPIO you need in the iomuxc node.<br>
<pre>
&iomuxc {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_hog>;
 
pinctrl_hog: hoggrp {
fsl,pins = <
/* Add your GPIO definitions here */
>;
};
…
};
</pre>
 
| VAR-SOM-MX93=
Edit arch/arm64/boot/dts/freescale/imx93-var-som-symphony.dts and add the definition for the GPIO you need in the iomuxc node.<br>
<pre>
&iomuxc {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_hog>;
 
pinctrl_hog: hoggrp {
fsl,pins = <
/* Add your GPIO definitions here */
>;
};
…
};
};
</pre>
</pre>
|
 
Edit arch/arm64/boot/dts/freescale/fsl-imx8qm-var-som.dts and add the definition for the GPIO you need in the iomuxc node.<br>
| VAR-SOM-MX8X=
Edit arch/arm64/boot/dts/freescale/fsl-imx8qxp-var-som-common.dtsi and add the definition for the GPIO you need in the iomuxc node.<br>
<pre>
<pre>
&iomuxc {
&iomuxc {
Line 62: Line 210:
pinctrl-0 = <&pinctrl_hog>;
pinctrl-0 = <&pinctrl_hog>;


imx8qm-var-som {
imx8qxp-var-som {
pinctrl_hog: hoggrp {
pinctrl_hog: hoggrp {
fsl,pins = <
fsl,pins = <
Line 75: Line 223:


=== Device Tree GPIO attribute ===
=== Device Tree GPIO attribute ===
If you look at the pin control definitions in arch/arm64/boot/dts/freescale/{{#ifeq: {{#var:HARDWARE_NAME}}|VAR-SOM-MX8X|imx8qxp-var-som-common.dtsi|fsl-imx8qm-var-som.dtsi}} in the Linux kernel source tree, the number to the right of the pin mux macro can be used for additional attributes like pull-up, slew rate, open drain, drive strength, etc.<br>
If you look at the pin control definitions in arch/arm64/boot/dts/{{#switch: {{#var:HARDWARE_NAME}} | VAR-SOM-MX8=freescale/{{#var:DTB_PREFIX|fsl-imx8qm-var-som}}.dts | DART-MX8M={{#ifeq: {{#var:YOCTO_NAME}} | Morty |variscite/imx8m-var-dart-common.dtsi|freescale/{{#var:DTB_PREFIX|fsl-imx8mq-var-dart}}{{#ifeq: {{#sub:{{#var:KERNEL_VER}}|0|2}} | 4. | -common | }}.dtsi}}| DART-MX8M-MINI=freescale/{{#var:DTB_PREFIX|fsl-imx8mm-var-dart}}.dts | VAR-SOM-MX8M-NANO=freescale/{{#var:DTB_PREFIX|fsl-imx8mn-var-som}}.dts | DART-MX8M-PLUS=freescale/imx8mp-var-dart.dts | VAR-SOM-MX8X=freescale/{{#var:DTB_PREFIX|fsl-imx8qxp-var-som}}.dts}} in the Linux kernel source tree, the number to the right of the pin mux macro can be used for additional attributes like pull-up, slew rate, open drain, drive strength, etc.<br>
This value is written to the IOMUXD register of the relevant pad.<br>
This value is written to the IOMUXC_SW_PAD_CTRL_ register of the relevant pin.<br>
Please consult the SOC reference manual for details about the relevant register.
Please consult the SOC reference manual for details about the relevant register.


Latest revision as of 09:37, 8 May 2023

Kernel Device Tree GPIO configuration

Device Tree GPIO files

Pin Func files

Adding only the one with the GPIO4_IO2 suffix (function) to your dts file will let you use the pin as GPIO.

Define a pin as GPIO in the kernel Device Tree

You need to add the relevant definitions to your device tree, as explained in the Pin Func files section above.


Device Tree GPIO attribute

If you look at the pin control definitions in arch/arm64/boot/dts/ in the Linux kernel source tree, the number to the right of the pin mux macro can be used for additional attributes like pull-up, slew rate, open drain, drive strength, etc.
This value is written to the IOMUXC_SW_PAD_CTRL_ register of the relevant pin.
Please consult the SOC reference manual for details about the relevant register.

U-Boot GPIO

In U-Boot, GPIO pins can be configured and manipulated using the "gpio" command. This command provides various options to configure the GPIO pins, set their direction (input or output), and toggle their values.

Installation

To enable the "gpio" command line tool in U-Boot, the defconfig file must have the following line: 

CONFIG_CMD_GPIO=y

Usage

=> gpio help
gpio - query and control gpio pins

Usage:
gpio <input|set|clear|toggle> <pin>
   - input/set/clear/toggle the specified pin
gpio status [-a] [<bank> | <pin>]  - show [all/claimed] GPIOs


Switch the GPIO pin to input mode: 

=> gpio input <pin>


Switch the GPIO pin to output mode and set its value to 1: 

=> gpio set <pin>


Switch the GPIO pin to output mode and set its value to 0: 

=> gpio clear <pin>


Switch the GPIO pin to output mode and toggle its value: 

=> gpio toggle <pin>


Display the status of one or multiple GPIOs: 

=> gpio status

By default only claimed GPIOs are displayed. To show unclaimed GPIOs, the -a parameter must be used: 

=> gpio status -a

gpio status command output fields are: 

<name>: <function>: <value> [x] <label>

function can take the following values:

  • output: pin configured in gpio output, the value indicates the pin’s level
  • input: pin configured in gpio input, the value indicates the pin’s level
  • func: pin configured in alternate function, followed by the label which shows pinmuxing label.
  • unused: pin not configured

[x] or [ ] indicate, respectively, if the gpio is used or not.
label shows the gpio label.

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This page was last edited on 8 May 2023, at 09:37.

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