DART-MX8M-PLUS Display: Difference between revisions
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To support a custom LVDS panel you should make several modifications.<br> | To support a custom LVDS panel you should make several modifications.<br> | ||
The following code references Variscite panel in arch/arm64/boot/dts/freescale/{{#var:DEFAULT_DTB}} under kernel source tree | The following code references Variscite panel in arch/arm64/boot/dts/freescale/{{#replace:{{#var:DEFAULT_DTB}}|.dtb|.dts}} under kernel source tree | ||
<pre> | <pre> | ||
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}; | }; | ||
</pre> | </pre> | ||
</ | |||
{{#ifexpr: {{#var:YOCTO_VERSION}} > 3.0 | | |||
= Known issues and limitations = | |||
Due to limited video PLL frequency points on NXP i.MX8MP, the current LVDS driver implementations only supports 74.25 MHz for single channel LVDS and 148.5 MHz for dual channel LVDS. | |||
To workaround this limitation, some manual adjustments may be implemented. | |||
The file arch/arm64/boot/dts/freescale/imx8mp.dtsi sets video_pll1_out to 1039500000000 (1039.5 MHz). | |||
The media_ldb_root_clk (parent of the LVDS clock) is provided by dividing video_pll1_out for a reasonable integer value. | |||
The LVDS clock is always given by media_ldb_root_clk / 7. | |||
Let's assume we want to achieve 70 MHz, the target value for media_ldb_root_clk is 70 MHz * 7 = 490 MHz | |||
Multiplying media_ldb_root_clk for a reasonable integer number (let's say 2), we get video_pll1_out: 490 MHz * 2 = 980 MHz. | |||
Now we have to force video_pll1_out to provide this specific value (980000000). | |||
* we need to update video_pll1_out with this new value in the ''clock-controller'' node of the file arch/arm64/boot/dts/freescale/imx8mp.dtsi | |||
* we need to introduce a clock setting providing this value in the file drivers/clk/imx/clk-pll14xx.c | |||
The table ''imx_pll1443x_tbl'' provides the lines with the following set of values | |||
rate, mdiv, pdiv, sdiv, kdiv | |||
These values are part of the formula | |||
rate = 24 MHz * (mdiv + kdiv / 65536) / (pdiv * 2 ^ sdiv) | |||
Let's make things easy and assume kdiv = 0 and sdiv = 1. | |||
In order to get a rate of 980 MHz we can just add the following line in the table ''imx_pll1443x_tbl'' (keeping the rate in descending order) | |||
(980000000U, 245, 3, 1, 0) | |||
As last step, at the end of the function ''imx8mp_ldb_encoder_atomic_check'' in the driver drivers/gpu/drm/imx/imx8mp-ldb.c, the following lines must be commented out | |||
<syntaxhighlight lang="c"> | |||
/* | |||
* Due to limited video PLL frequency points on i.MX8mp, | |||
* we do mode fixup here in case any mode is unsupported. | |||
*/ | |||
if (ldb->dual) | |||
mode->clock = mode->clock > 100000 ? 148500 : 74250; | |||
else | |||
mode->clock = 74250; | |||
</syntaxhighlight> | |||
|}} | |||
Revision as of 00:37, 22 April 2023
HDMI, MIPI-DSI and LVDS
DART-MX8M-PLUS SoC supports LVDS, HDMI and MIPI-DSI interfaces.
DART-MX8M-PLUS carrier board comes with LVDS and HDMI connectors, so you can easily connect LVDS and HDMI displays.
Connecting MIPI-DSI display to DART-MX8M-PLUS carrier board requires designing a custom connector.
Adding custom LVDS panel
DART-MX8M-PLUS evaluation kit comes with 800x480 LCD panel. DART-MX8M-PLUS DTS file was created with this panel in mind.
To support a custom LVDS panel you should make several modifications.
The following code references Variscite panel in arch/arm64/boot/dts/freescale/imx8mp-var-dart.dts under kernel source tree
panel {
compatible = "sgd,gktw70sdae4se", "panel-lvds";
backlight = <&backlight>;
width-mm = <153>;
height-mm = <87>;
label = "gktw70sdae4se";
data-mapping = "jeida-24";
status = "okay";
panel-timing {
clock-frequency = <33000000>;
hactive = <800>;
vactive = <480>;
hback-porch = <40>;
hfront-porch = <40>;
vback-porch = <29>;
vfront-porch = <13>;
hsync-len = <48>;
vsync-len = <3>;
hsync-active = <0>;
vsync-active = <0>;
de-active = <1>;
};
...
};
&ldb {
status = "okay";
lvds-channel@0 {
fsl,data-mapping = "jeida";
fsl,data-width = <24>;
status = "okay";
...
};
You should modify panel "data-mapping" and "display-timings" properties to match your panel specification.
You should also modify ldb (internal LVDS bridge) "fsl,data-mapping" and "fsl,data-width" properties to match your panel specification.
Supported "data-mapping" values are "jeida-18", "jeida-24" and "vesa-24".
Supported "fsl,data-mapping" values are "jeida", and "spwg".
Supported "fsl,data-width" values are <18>, and <24>.
For dual channel LVDS panels add fsl,dual-channel property to ldb node, as in the example below:
&ldb {
status = "okay";
fsl,dual-channel;
lvds-channel@0 {
fsl,data-mapping = "jeida";
fsl,data-width = <24>;
status = "okay";
...
};