DART-MX8M UART: Difference between revisions
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{{ | <!-- Set release according to "release" parameter in URL and use RELEASE_SUMO_V1.0_DART-MX8M as default | ||
--> {{INIT_RELEASE_PARAM|RELEASE_SUMO_V1.0_DART-MX8M}}<!-- | |||
= DART-MX8M UART Overview = | --> {{#lst:Yocto_Platform_Customization|{{#var:RELEASE_PARAM}}}} <!-- | ||
--> {{#lst:B2QT_Platform_Customization|{{#var:RELEASE_PARAM}}}} <!-- | |||
UART1 is connected to debug console | --> {{#lst:Android_Platform_Customization|{{#var:RELEASE_PARAM}}}} <!-- | ||
On | --> {{#lst:Debian_Platform_Customization|{{#var:RELEASE_PARAM}}}} <!-- | ||
--> {{PageHeader|{{#var:HARDWARE_NAME}} UART}} {{DocImage|category1=Yocto|category2=Android}}[[Category:Debian]][[Category:{{#var:HARDWARE_NAME}}]] __toc__ | |||
<!-- Set local variables | |||
--> {{#vardefine:SHOW_DART_SECTION | <!-- | |||
--> {{#switch:{{#var:HARDWARE_NAME}} | <!-- | |||
--> DART-MX8M | <!-- | |||
--> DART-MX8M-PLUS | <!-- | |||
--> DART-MX8M-MINI = true | <!-- | |||
--> false <!-- | |||
--> }} <!-- | |||
--> }} <!-- | |||
--> {{#vardefine:SHOW_SYMPHONY_SECTION | <!-- | |||
--> {{#switch:{{#var:HARDWARE_NAME}} | <!-- | |||
--> DART-MX8M = false | <!-- | |||
--> true <!-- | |||
--> }} <!-- | |||
--> }} <!-- | |||
--> {{#vardefine:SYMPHONY_SOM_NAME | <!-- | |||
--> {{#switch:{{#var:HARDWARE_NAME}} | <!-- | |||
--> DART-MX8M-MINI = VAR-SOM-MX8M-MINI | <!-- | |||
--> DART-MX8M-PLUS = VAR-SOM-MX8M-PLUS | <!-- | |||
--> {{#var:HARDWARE_NAME}} <!-- | |||
--> }} <!-- | |||
--> }} <!-- | |||
--> {{#vardefine:DTS_PATH | <!-- | |||
--> {{#switch:{{#var:ANDROID_NAME}} | <!-- | |||
--> Pie = {{#var:BUILD_FOLDER}}/{{#var:BUILD_FOLDER_ANDROID}}/variscite/kernel_imx/ | <!-- | |||
--> }} <!-- | |||
--> }} <!-- | |||
--> {{#vardefine:DTS_NAME | <!-- | |||
--> {{#switch:{{#var:HARDWARE_NAME}} | <!-- | |||
--> DART-MX8M = {{#ifeq: {{#var:YOCTO_NAME}}|Morty|variscite/imx8m-var-dart-common.dtsi|freescale/fsl-imx8mq-var-dart-common.dtsi}} | <!-- | |||
--> DART-MX8M-MINI = freescale/fsl-imx8mm-var-dart.dts | <!-- | |||
--> VAR-SOM-MX8M-MINI = freescale/fsl-imx8mn-var-som.dts | <!-- | |||
--> DART-MX8M-PLUS = freescale/imx8mp-var-dart.dts | <!-- | |||
--> VAR-SOM-MX8M-PLUS = freescale/imx8mp-var-som.dts | <!-- | |||
--> {{#var:HARDWARE_NAME}} <!-- | |||
--> }} <!-- | |||
--> }} | |||
= UART Overview = | |||
{{#ifeq: {{#var:SHOW_DART_SECTION}}|true| | |||
On '''{{#var:HARDWARE_NAME}}''' all 4 UARTs are enabled by default.<br> | |||
UART1 is connected to debug console.<br> | |||
UART2 and UART3 are connected to J12 header on VAR-DT8MCustomBoard.<br> | |||
UART4 is connected to Bluetooth module.<br> | |||
On {{#var:HARDWARE_NAME}} SoMs without WIFI/BT module UART4 is also connected to J12 header.<br> | |||
See the [https://www.variscite.com/wp-content/uploads/2018/04/VAR-DT8MCustomBoard-Datasheet.pdf carrier board datasheet] for the exact pinout.<br> | See the [https://www.variscite.com/wp-content/uploads/2018/04/VAR-DT8MCustomBoard-Datasheet.pdf carrier board datasheet] for the exact pinout.<br> | ||
Only UART4 has RTS and CTS lines. | Only UART4 has RTS and CTS lines. | ||
|}} | |||
{{#ifeq: {{#var:SHOW_SYMPHONY_SECTION}}|true| | |||
On '''{{#var:SYMPHONY_SOM_NAME}}''' all 4 UARTs are enabled by default.<br> | |||
{{#ifeq: {{#var:SYMPHONY_SOM_NAME}}|VAR-SOM-MX8M-PLUS| | |||
UART1 is connected to J18 header.<br> | |||
UART2 is connected to to debug console.<br> | |||
UART3 is connected to Bluetooth module.<br> | |||
UART4 is connected to J18 header.<br> | |||
On {{#var:SYMPHONY_SOM_NAME}} SoMs without WIFI/BT module UART3 is also connected to J18 header.<br> | |||
See the [https://www.variscite.com/wp-content/uploads/2019/07/Symphony-Board-Datasheet.pdf carrier board datasheet] for the exact pinout.<br> | |||
Only UART3 has RTS and CTS lines. | |||
| | |||
UART1 is connected to J30 header on Symphony-Board (located on the back of the board).<br> | |||
UART2 is connected to Bluetooth module.<br> | |||
UART3 is connected to J18 header.<br> | |||
UART4 is connected to debug console.<br> | |||
On {{#var:SYMPHONY_SOM_NAME}} SoMs without WIFI/BT module UART2 is also connected to J18 header.<br> | |||
See the [https://www.variscite.com/wp-content/uploads/2019/07/Symphony-Board-Datasheet.pdf carrier board datasheet] for the exact pinout.<br> | |||
Only UART2 has RTS and CTS lines. | |||
|}}}} | |||
= UART naming under Linux = | = UART naming under Linux = | ||
The Linux devices corresponding to UART1 - UART4 are /dev/ttymxc0 - /dev/ttymxc3 respectively. | The Linux devices corresponding to UART1 - UART4 are /dev/ttymxc0 - /dev/ttymxc3 respectively. | ||
= Testing UART2 = | {{#ifeq: {{#var:SHOW_DART_SECTION}}|true| | ||
= Testing UART2 on {{#var:HARDWARE_NAME}} = | |||
Short J12.4 and J12.6 pins and run the following commands: | Short J12.4 and J12.6 pins and run the following commands: | ||
Line 23: | Line 89: | ||
For each time you run this echo command the "hello" string should appear on the terminal. | For each time you run this echo command the "hello" string should appear on the terminal. | ||
= Testing UART3 = | = Testing UART3 on {{#var:HARDWARE_NAME}} = | ||
Short J12.11 and J12.13 pins and run the following commands: | Short J12.11 and J12.13 pins and run the following commands: | ||
Line 32: | Line 98: | ||
</pre> | </pre> | ||
For each | For each invocation of echo command the "hello" string should appear on the terminal. | ||
|}} | |||
{{#ifeq: {{#var:SHOW_SYMPHONY_SECTION}}|true| | |||
= Testing UART3 on {{#var:SYMPHONY_SOM_NAME}} = | |||
Short J18.3 and J18.5 pins and run the following commands: | |||
<pre> | |||
stty -F /dev/ttymxc2 -echo -onlcr 115200 | |||
cat /dev/ttymxc2 & | |||
echo hello > /dev/ttymxc2 | |||
</pre> | |||
For each invocation of echo command the "hello" string should appear on the terminal. | |||
|}} | |||
= Disabling UART2 = | = Disabling UART2 = | ||
To disable UART2 edit arch/arm64/boot/dts/ | To disable UART2 on '''{{#var:HARDWARE_NAME}}''' edit {{#var:DTS_PATH}}arch/arm64/boot/dts/{{#var:DTS_NAME}} under kernel source directory and modify | ||
<pre> | <pre> | ||
Line 55: | Line 135: | ||
Other UARTs can be disabled in the same manner. | Other UARTs can be disabled in the same manner. | ||
{{#ifeq: {{#var:SYMPHONY_SOM_NAME}}|VAR-SOM-MX8M-MINI| | |||
To disable UART2 on '''{{#var:SYMPHONY_SOM_NAME}}''' edit {{#var:DTS_PATH}}arch/arm64/boot/dts/freescale/freescale/fsl-imx8mm-var-som.dts in the same manner. | |||
|}} | |||
= Configuring RS485 Half-Duplex = | |||
{{#lst:Yocto_Platform_Customization|RS485_HALF_DUPLEX}} |
Latest revision as of 15:58, 7 February 2023
This page is using the default release RELEASE_SUMO_V1.0_DART-MX8M.
To view this page for a specific Variscite SoM and software release, please follow these steps:
- Visit variwiki.com
- Select your SoM
- Select the software release
UART Overview
On DART-MX8M all 4 UARTs are enabled by default.
UART1 is connected to debug console.
UART2 and UART3 are connected to J12 header on VAR-DT8MCustomBoard.
UART4 is connected to Bluetooth module.
On DART-MX8M SoMs without WIFI/BT module UART4 is also connected to J12 header.
See the carrier board datasheet for the exact pinout.
Only UART4 has RTS and CTS lines.
UART naming under Linux
The Linux devices corresponding to UART1 - UART4 are /dev/ttymxc0 - /dev/ttymxc3 respectively.
Testing UART2 on DART-MX8M
Short J12.4 and J12.6 pins and run the following commands:
stty -F /dev/ttymxc1 -echo -onlcr 115200 cat /dev/ttymxc1 & echo hello > /dev/ttymxc1
For each time you run this echo command the "hello" string should appear on the terminal.
Testing UART3 on DART-MX8M
Short J12.11 and J12.13 pins and run the following commands:
stty -F /dev/ttymxc2 -echo -onlcr 115200 cat /dev/ttymxc2 & echo hello > /dev/ttymxc2
For each invocation of echo command the "hello" string should appear on the terminal.
Disabling UART2
To disable UART2 on DART-MX8M edit arch/arm64/boot/dts/freescale/fsl-imx8mq-var-dart-common.dtsi under kernel source directory and modify
&uart2 { ... status = "okay"; };
to
&uart2 { ... status = "disabled"; };
Other UARTs can be disabled in the same manner.
Configuring RS485 Half-Duplex
Each UART can be configured for RS485 Half-Duplex mode by using a GPIO pin to drive the receive and transmit enable inputs. This can be configured in the device tree by making the following changes to the uart node and replacing X, Y & Z with the proper values:
&uartX { /* Add RS485 properties to uartX */ pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uartX>, <&pinctrl_uartX_rs485>; /* Add RS485 GPIO pinctrl */ rts-gpios = <&gpioY Z GPIO_ACTIVE_LOW>; /* Add rts-gpios property */ linux,rs485-enabled-at-boot-time; /* Enable RS485 at boot time to skip using TIOCSRS485 ioctl */ status = "okay"; };
Next, configure the RS485 GPIO pin by adding pinctrl_uartX_rs485
to iomuxc
. Replace X, GPIO_PIN_FUNCTION, and GPIO_PIN_SETTINGS with the proper values:
&iomuxc { pinctrl_uartX_rs485: uartXrs485 { fsl,pins = < GPIO_PIN_FUNCTION GPIO_PIN_SETTINGS >; }; };
Note: For more information about configuring pins, please see i.MX Device Tree Pinmux Settings Guide
After making these changes, RS485 mode will be enabled by default and can be verified from the console by running the commands below. Replace N with the proper value, which is typically X-1 relative to the device tree node uartX
:
# stty -F /dev/ttymxcN -echo -onlcr 115200 # echo hello > /dev/ttymxcN
The below logic analyzer capture shows the RS485 RX/TX enable line toggling when writing to the UART:
Please refer to the Linux device tree bindings for more RS485 configuration options.