VAR-SOM-MX8M-MINI-Rev10: Difference between revisions
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This tutorial shows how to adjust kernel DTS files for VAR-SOM-MX8M-MINI/NANO | This tutorial shows how to adjust kernel DTS files for VAR-SOM-MX8M-MINI/NANO revision 1.0, as starting from Yocto Dunfell this old SOM revision is not supported "out of the box". | ||
= On Symphony-Board 1.4a and above = | = On Symphony-Board 1.4a and above = | ||
| Line 89: | Line 89: | ||
Apply the following patch to imx8mn-var-som-symphony-legacy.dts: | Apply the following patch to imx8mn-var-som-symphony-legacy.dts: | ||
<syntaxhighlight lang="diff"> | <syntaxhighlight lang="diff"> | ||
--- arch/arm64/boot/dts/freescale/ | --- arch/arm64/boot/dts/freescale/imx8mn-var-som-symphony-legacy.dts 2020-12-30 23:28:09.881966875 +0200 | ||
+++ arch/arm64/boot/dts/freescale/ | +++ arch/arm64/boot/dts/freescale/imx8mn-var-som-symphony-legacy-rev10.dts 2021-01-10 09:22:13.465180492 +0200 | ||
@@ -10,7 +10,21 @@ | @@ -10,7 +10,21 @@ | ||
model = "Variscite VAR-SOM-MX8M- | model = "Variscite VAR-SOM-MX8M-NANO on Symphony-Board 1.4 and below"; | ||
}; | }; | ||
| Line 100: | Line 100: | ||
+ pinctrl_usdhc2_gpio: usdhc2grpgpio { | + pinctrl_usdhc2_gpio: usdhc2grpgpio { | ||
+ fsl,pins = < | + fsl,pins = < | ||
+ | + MX8MN_IOMUXC_SD2_CD_B_GPIO2_IO12 0xc1 | ||
+ >; | + >; | ||
+ }; | + }; | ||
| Line 106: | Line 106: | ||
+ pinctrl_extcon: extcongrp { | + pinctrl_extcon: extcongrp { | ||
+ fsl,pins = < | + fsl,pins = < | ||
+ | + MX8MN_IOMUXC_GPIO1_IO10_GPIO1_IO10 0x16 | ||
+ >; | + >; | ||
+ }; | + }; | ||
Latest revision as of 11:47, 7 February 2022
VAR-SOM-MX8M-MINI/NANO Revision 1.0 Support
This tutorial shows how to adjust kernel DTS files for VAR-SOM-MX8M-MINI/NANO revision 1.0, as starting from Yocto Dunfell this old SOM revision is not supported "out of the box".
On Symphony-Board 1.4a and above
Apply the following patch to imx8mm-var-som-symphony.dts:
--- arch/arm64/boot/dts/freescale/imx8mm-var-som-symphony.dts 2020-12-30 23:16:31.021169623 +0200
+++ arch/arm64/boot/dts/freescale/imx8mm-var-som-symphony-rev10.dts 2021-01-10 09:16:31.586865372 +0200
@@ -214,7 +214,7 @@
pinctrl_usdhc2_gpio: usdhc2grpgpio {
fsl,pins = <
- MX8MM_IOMUXC_GPIO1_IO10_GPIO1_IO10 0xc1
+ MX8MM_IOMUXC_SD2_CD_B_GPIO2_IO12 0xc1
>;
};
@@ -487,7 +487,7 @@
pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;
pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>;
pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>;
- cd-gpios = <&gpio1 10 GPIO_ACTIVE_LOW>;
+ cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>;
bus-width = <4>;
vmmc-supply = <®_usdhc2_vmmc>;
status = "okay";
On Symphony-Board 1.4 and below
Apply the following patch to imx8mm-var-som-symphony-legacy.dts:
--- arch/arm64/boot/dts/freescale/imx8mm-var-som-symphony-legacy.dts 2020-12-30 23:28:09.881966875 +0200
+++ arch/arm64/boot/dts/freescale/imx8mm-var-som-symphony-legacy-rev10.dts 2021-01-10 09:22:13.465180492 +0200
@@ -10,7 +10,21 @@
model = "Variscite VAR-SOM-MX8M-MINI on Symphony-Board 1.4 and below";
};
-&usbotg1 {
- /delete-property/ extcon;
+&iomuxc {
+ pinctrl_usdhc2_gpio: usdhc2grpgpio {
+ fsl,pins = <
+ MX8MM_IOMUXC_SD2_CD_B_GPIO2_IO12 0xc1
+ >;
+ };
+
+ pinctrl_extcon: extcongrp {
+ fsl,pins = <
+ MX8MM_IOMUXC_GPIO1_IO10_GPIO1_IO10 0x16
+ >;
+ };
+};
+
+&usdhc2 {
+ cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>;
};
CAN bus
See also: VAR-SOM-MX8M-MINI/NANO Rev 1.0/1.1/1.2 CAN bus support