VAR-SOM-MX8M-MINI-CAN

VAR-SOM-MX8M-MINI/NANO Rev 1.0/1.1/1.2 CAN Bus support

Introduction

On VAR-SOM-MX8M-MINI/NANO revision 1.3 some changes were introduced to improve the performance of the MCP251XFD CAN controller.

Starting from the following SW releases the kernel DTS files are synchronized with SOM revision 1.3:
Yocto Dunfell releases: dunfell-fslc-5.4-2.1.x-mx8mm-v1.3 & dunfell-fslc-5.4-2.1.x-mx8mn-v1.2
Android 10 releases q10.0.0_1.0.0-ga_dart-mx8mm_v1.6 & android-10.0.0_2.3.0-ga_mx8mn_v1.4

Some adjustments are necessary for older SOM revisions to ensure the correct CAN controller operation.
This tutorial shows how to adjust the kernel DTS files for VAR-SOM-MX8M-MINI/NANO revisions 1.0/1.1/1.2.

On VAR-SOM-MX8M-MINI

Apply the following patch to imx8mm-var-som.dtsi:

diff --git a/arch/arm64/boot/dts/freescale/imx8mm-var-som.dtsi b/arch/arm64/boot/dts/freescale/imx8mm-var-som.dtsi
index 9f648ebff447..9f60caecd7ce 100644
--- a/arch/arm64/boot/dts/freescale/imx8mm-var-som.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8mm-var-som.dtsi
@@ -14,7 +14,7 @@
 		compatible = "fixed-clock";
 		#clock-cells = <0>;
 		/* On SOM revions 1.2 and below the frequency should be 20000000 */
-		clock-frequency = <40000000>;
+		clock-frequency = <20000000>;
 		clock-output-names = "can_osc";
 	};
 
@@ -114,10 +114,8 @@
 		clocks = <&can0_osc>;
 		interrupt-parent = <&gpio1>;
 		interrupts = <5 IRQ_TYPE_LEVEL_LOW>;
-		/* On SOM revions 1.2 and below RX-INT GPIO is not available */
-		microchip,rx-int-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>;
 		/* On SOM revions 1.2 and below the spi-max-frequency should be 10000000 */
-		spi-max-frequency = <20000000>;
+		spi-max-frequency = <10000000>;
 		status = "okay";
 	};
 
@@ -172,8 +170,6 @@
 	pinctrl_can: cangrp {
 		fsl,pins = <
 			MX8MM_IOMUXC_GPIO1_IO05_GPIO1_IO5		0x16 	/* CAN INT */
-			MX8MM_IOMUXC_SD2_CD_B_GPIO2_IO12		0x16	/* CAN RX-INT - SOM rev1.3+ only */
-			MX8MM_IOMUXC_GPIO1_IO15_GPIO1_IO15		0x16	/* CAN TX-INT - SOM rev1.3+ only */
 		>;
 	};

On VAR-SOM-MX8M-NANO

Apply the following patch to imx8mn-var-som.dtsi:

diff --git a/arch/arm64/boot/dts/freescale/imx8mn-var-som.dtsi b/arch/arm64/boot/dts/freescale/imx8mn-var-som.dtsi
index 66d7b020b857..6af877e6aa8f 100644
--- a/arch/arm64/boot/dts/freescale/imx8mn-var-som.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8mn-var-som.dtsi
@@ -14,7 +14,7 @@
 		compatible = "fixed-clock";
 		#clock-cells = <0>;
 		/* On SOM revions 1.2 and below the frequency should be 20000000 */
-		clock-frequency = <40000000>;
+		clock-frequency = <20000000>;
 		clock-output-names = "can_osc";
 	};
 
@@ -124,10 +124,8 @@
 		clocks = <&can0_osc>;
 		interrupt-parent = <&gpio1>;
 		interrupts = <5 IRQ_TYPE_LEVEL_LOW>;
-		/* On SOM revions 1.2 and below RX-INT GPIO is not available */
-		microchip,rx-int-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>;
 		/* On SOM revions 1.2 and below the spi-max-frequency should be 10000000 */
-		spi-max-frequency = <20000000>;
+		spi-max-frequency = <10000000>;
 		status = "okay";
 	};
 
@@ -193,8 +191,6 @@
 	pinctrl_can: cangrp {
 		fsl,pins = <
 			MX8MN_IOMUXC_GPIO1_IO05_GPIO1_IO5		0x1c0	/* CAN-INT */
-			MX8MN_IOMUXC_SD2_CD_B_GPIO2_IO12		0x16	/* CAN RX-INT - SOM rev1.3+ only */
-			MX8MN_IOMUXC_GPIO1_IO15_GPIO1_IO15		0x16	/* CAN TX-INT - SOM rev1.3+ only */
 		>;
 	};