MX8 SPI: Difference between revisions
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--> {{PageHeader|{{#var:HARDWARE_NAME}} SPI}} {{DocImage|category1=Yocto|category2= | --> {{PageHeader|{{#var:HARDWARE_NAME}} SPI}} {{DocImage|category1=Yocto|category2={{#var:HARDWARE_NAME}}}} __toc__ | ||
= Kernel configuration= | = Overview = | ||
In this example we show how to configure and test SPI on {{#var:HARDWARE_NAME}}. | |||
The SPI pins on external connector J16 will be used used to run SPI loopback test. | |||
= Kernel configuration = | |||
Verify that the i.MX LPSPI driver (CONFIG_SPI_FSL_LPSPI) is enabled in your kernel configuration: | Verify that the i.MX LPSPI driver (CONFIG_SPI_FSL_LPSPI) is enabled in your kernel configuration: | ||
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* In menuconfig: Device Drivers -> SPI support -> <*> User mode SPI device driver support<br> | * In menuconfig: Device Drivers -> SPI support -> <*> User mode SPI device driver support<br> | ||
== Check spidev node == | |||
== | |||
{{#ifeq: {{#var:HARDWARE_NAME}} | VAR-SOM-MX8X | | |||
Check that spidev node exists and is enabled in arch/arm64/boot/dts/freescale/imx8qxp-var-som-common.dtsi.<br> | |||
GPIO1_0 will be used in this example to control SPI CS0. | |||
<pre> | |||
&lpspi2 { | |||
#address-cells = <1>; | |||
#size-cells = <0>; | |||
pinctrl-names = "default"; | |||
pinctrl-0 = <&pinctrl_lpspi2 &pinctrl_lpspi2_cs>; | |||
cs-gpios = <&gpio1 0 GPIO_ACTIVE_LOW>; | |||
status = "okay"; | |||
spidev@0 { | |||
compatible = "spidev"; | |||
spi-max-frequency = <12000000>; | |||
reg = <0>; | |||
status = "disabled"; | |||
}; | |||
}; | |||
</pre> | |||
| | |||
Check that spidev node exists and is enabled in arch/arm64/boot/dts/freescale/imx8qm-var-som.dtsi.<br> | |||
GPIO3_24 will be used in this example to control SPI CS0. | |||
<pre> | <pre> | ||
& | &lpspi1 { | ||
#address-cells = <1>; | #address-cells = <1>; | ||
#size-cells = <0>; | #size-cells = <0>; | ||
fsl,spi-num-chipselects = <1>; | |||
pinctrl-0 = <& | pinctrl-names = "default"; | ||
pinctrl-0 = <&pinctrl_lpspi1 &pinctrl_lpspi1_cs>; | |||
cs-gpios = <&gpio3 24 0>; | |||
status = "okay"; | status = "okay"; | ||
spidev@0 { | spidev@0 { | ||
compatible = "spidev"; | |||
spi-max-frequency = <12000000>; | |||
reg = <0>; | |||
status = "okay"; | |||
}; | }; | ||
}; | }; | ||
</pre> | </pre> | ||
}} | |||
== | == Check configuration of SPI pins == | ||
{{#ifeq: {{#var:HARDWARE_NAME}} | | {{#ifeq: {{#var:HARDWARE_NAME}} | VAR-SOM-MX8X | | ||
<pre> | <pre> | ||
&iomuxc { | &iomuxc { | ||
imx8qxp-var-som { | |||
... | ... | ||
pinctrl_lpspi2: lpspi2grp { | |||
fsl,pins = < | fsl,pins = < | ||
SC_P_SPI2_SCK_ADMA_SPI2_SCK 0x0600004c | |||
SC_P_MCLK_IN0_ADMA_SPI2_SDI 0x0600004c | |||
SC_P_SPI2_SDO_ADMA_SPI2_SDO 0x0600004c | |||
>; | |||
}; | |||
pinctrl_lpspi2_cs: lpspi2csgrp { | |||
fsl,pins = < | |||
SC_P_SPI2_CS0_LSIO_GPIO1_IO00 0x21 | |||
>; | >; | ||
}; | }; | ||
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<pre> | <pre> | ||
&iomuxc { | &iomuxc { | ||
imx8qm-var-som { | |||
... | ... | ||
pinctrl_lpspi1: lpspi1grp { | |||
fsl,pins = < | |||
SC_P_ADC_IN3_DMA_SPI1_SCK 0x0600004c | |||
SC_P_ADC_IN4_DMA_SPI1_SDO 0x0600004c | |||
SC_P_ADC_IN5_DMA_SPI1_SDI 0x0600004c | |||
>; | |||
}; | |||
pinctrl_lpspi1_cs: lpspi1csgrp { | |||
fsl,pins = < | fsl,pins = < | ||
SC_P_ADC_IN6_LSIO_GPIO3_IO24 0x00000021 | |||
>; | >; | ||
}; | }; | ||
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= Recompile the kernel = | = Recompile the kernel = | ||
Reompile the kernel and device tree (if any changes were made to DTS and kernel configuration) and update the SOM. | |||
= Compile SPI test application = | = Compile SPI test application = | ||
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</pre> | </pre> | ||
== SPI | == SPI External Connector == | ||
SPI | SPI is accessible on the following EVK pins: | ||
* J16.2 - | * J16.2 - SCLK | ||
* J16.4 - | * J16.4 - SS0 | ||
* J16.6 - | * J16.6 - MOSI | ||
* J16.8 - | * J16.8 - MISO | ||
= Run SPI Test = | = Run SPI Test = | ||
Copy spidev_test binary to | Copy spidev_test binary to the SOM.<br> | ||
Loop | Loop MOSI and MISO by putting a jumper on J16.6 and J16.8<br> | ||
Run SPI test tool | Run SPI test tool | ||
<pre> | <pre> | ||
# ./spidev_test -v -D /dev/spidev0.0 | # ./spidev_test -v -D /dev/spidev0.0 | ||
</pre> | </pre> | ||
The output of successful test should look like this: | The output of successful test should look like this: | ||
<pre> | <pre> | ||
Line 121: | Line 145: | ||
RX | FF FF FF FF FF FF 40 00 00 00 00 95 FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF F0 0D | ......@....�..................�. | RX | FF FF FF FF FF FF 40 00 00 00 00 95 FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF F0 0D | ......@....�..................�. | ||
</pre> | </pre> | ||
Revision as of 17:33, 2 September 2019
Overview
In this example we show how to configure and test SPI on VAR-SOM-MX8X. The SPI pins on external connector J16 will be used used to run SPI loopback test.
Kernel configuration
Verify that the i.MX LPSPI driver (CONFIG_SPI_FSL_LPSPI) is enabled in your kernel configuration:
- In menuconfig: Device Drivers -> SPI support -> <*> Freescale i.MX LPSPI controller
Verify that the User mode SPI driver (CONFIG_SPI_SPIDEV) is enabled in your kernel configuration:
- In menuconfig: Device Drivers -> SPI support -> <*> User mode SPI device driver support
Check spidev node
Check that spidev node exists and is enabled in arch/arm64/boot/dts/freescale/imx8qxp-var-som-common.dtsi.
GPIO1_0 will be used in this example to control SPI CS0.
&lpspi2 { #address-cells = <1>; #size-cells = <0>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_lpspi2 &pinctrl_lpspi2_cs>; cs-gpios = <&gpio1 0 GPIO_ACTIVE_LOW>; status = "okay"; spidev@0 { compatible = "spidev"; spi-max-frequency = <12000000>; reg = <0>; status = "disabled"; }; };
Check configuration of SPI pins
&iomuxc { imx8qxp-var-som { ... pinctrl_lpspi2: lpspi2grp { fsl,pins = < SC_P_SPI2_SCK_ADMA_SPI2_SCK 0x0600004c SC_P_MCLK_IN0_ADMA_SPI2_SDI 0x0600004c SC_P_SPI2_SDO_ADMA_SPI2_SDO 0x0600004c >; }; pinctrl_lpspi2_cs: lpspi2csgrp { fsl,pins = < SC_P_SPI2_CS0_LSIO_GPIO1_IO00 0x21 >; }; ... }; };
Recompile the kernel
Reompile the kernel and device tree (if any changes were made to DTS and kernel configuration) and update the SOM.
Compile SPI test application
There's an SPI test utility in the kernel source tree: tools/spi/spidev_test.c
To cross compile it, use the following command:
$ $CC ./tools/spi/spidev_test.c -o ./spidev_test
SPI External Connector
SPI is accessible on the following EVK pins:
- J16.2 - SCLK
- J16.4 - SS0
- J16.6 - MOSI
- J16.8 - MISO
Run SPI Test
Copy spidev_test binary to the SOM.
Loop MOSI and MISO by putting a jumper on J16.6 and J16.8
Run SPI test tool
# ./spidev_test -v -D /dev/spidev0.0
The output of successful test should look like this:
spi mode: 0x20 bits per word: 8 max speed: 500000 Hz (500 KHz) TX | FF FF FF FF FF FF 40 00 00 00 00 95 FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF F0 0D | ......@....�..................�. RX | FF FF FF FF FF FF 40 00 00 00 00 95 FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF F0 0D | ......@....�..................�.