Android Camera: Difference between revisions

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*VAR-DT6CustomBoard:
*VAR-DT6CustomBoard:
CSI1 - MIPI Clock + 2 Data lanes are accessible via Carrier board header.<br>
CSI1 - MIPI Clock + 2 Data lanes are accessible via carrier board header.<br>
J13: MIPI - 2 Lane + CLK + I2C<br>
J13: MIPI - 2 Lane + CLK + I2C<br>
CSI0 - Parallel camera pins are accesible via carrier board header.<br>
CSI0 - Parallel camera pins are accesible via carrier board header.<br>
Line 25: Line 25:


*VAR-SOLOCustomBoard:
*VAR-SOLOCustomBoard:
CSI1 - MIPI Clock +4 Data lanes are accessible via Carrier board Headers.
CSI1 - MIPI Clock +4 Data lanes are accessible via carrier board Headers.
LVDS1 - LVDS Clock +3 Data lanes are accessible via Carrier board Headers (only 18 bit LCD can be interfaced)
J12: MIPI 2 Lane + CLK + I2C<br>
CSI0 - Parallel camera 8 bit pins are accesible via carrier board header.<br>
J8: Parallel - 8 bit + I2C<br>
For more details refer to: https://www.variscite.com/wp-content/uploads/2017/12/VAR-SOLOCustomBoard-Schematics.pdf <br>
 


For maximum, supported resolution and combinations refer to http://cache.freescale.com/files/training/doc/ftf/2014/FTF-CON-F0119.pdf page no 21 for more details and combination.
For maximum, supported resolution and combinations refer to http://cache.freescale.com/files/training/doc/ftf/2014/FTF-CON-F0119.pdf page no 21 for more details and combination.

Revision as of 20:18, 27 November 2018

VAR-SOM-MX6 - Camera

Overview

i.MX6 platforms are capable of handling multiple cameras.(With some restriction)
See page: 20 - 30 http://cache.freescale.com/files/training/doc/ftf/2014/FTF-CON-F0119.pdf
Android Application can leverage the use of multiple cameras for capturing the video frames.
VAR-SOM-MX6 / DART-MX6 / Solo-Dual have MIPI / Parallel camera support, available on the development board.

Hardware Availability

  • VAR-SOM-MX6 Custom board:

CSI1 - MIPI Clock + 4 Data lanes are accessible via Carrier board header.
J17: MIPI - 4 Lane + CLK + I2C + GPIOs
CSI0 - Parallel camera pins are accesible via carrier board header.
J18: Parallel - 8 bit + I2C

For more details refer to: https://www.variscite.com/wp-content/uploads/2017/12/V2_VAR-MX6CustomBoard-Schematics.pdf
MIPI Camera Accessories Required: https://www.variscite.com/products/accessories/i-mx6-camera-board/

  • VAR-DT6CustomBoard:

CSI1 - MIPI Clock + 2 Data lanes are accessible via carrier board header.
J13: MIPI - 2 Lane + CLK + I2C
CSI0 - Parallel camera pins are accesible via carrier board header.
J11: Parallel - 16 bit + I2C
For more details refer to: https://www.variscite.com/wp-content/uploads/2017/11/VAR-DT6CustomBoard-Schematics.pdf

  • VAR-SOLOCustomBoard:

CSI1 - MIPI Clock +4 Data lanes are accessible via carrier board Headers. J12: MIPI 2 Lane + CLK + I2C
CSI0 - Parallel camera 8 bit pins are accesible via carrier board header.
J8: Parallel - 8 bit + I2C
For more details refer to: https://www.variscite.com/wp-content/uploads/2017/12/VAR-SOLOCustomBoard-Schematics.pdf


For maximum, supported resolution and combinations refer to http://cache.freescale.com/files/training/doc/ftf/2014/FTF-CON-F0119.pdf page no 21 for more details and combination.

IMX6 Image Processing Chain.png

Note: i.MX6 platform doesn't have the SOC based Image Signal Processing (ISP) unit to convert bayer data to RGB and YUV.
Hence i.MX6 platform relies on MIPI camera to convert the bayer data to YUV format.