From Variscite Wiki
Revision as of 21:23, 13 April 2022 by Alex (talk | contribs)

Supporting the i.MX7-Dual, the VAR-SOM-MX7 allows designers to use a single System on Module in a broad range of applications to achieve short time-to-market for their current innovations, while still accommodating potential R&D directions and marketing opportunities. This versatile solution’s -20 to 85 °C temperature range and Dual CAN support is ideal for industrial applications.

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Yocto <rssbutton height=20 width=20></rssbutton>
Dunfell (kernel 5.4.142)

Thud (kernel 4.14.78)

Sumo (kernel 4.9.88)

Rocko (kernel 4.9.11)

Pyro (kernel 4.1.15)

Morty (kernel 4.1.15)

Legacy releases

Debian <rssbutton height=20 width=20></rssbutton>
Bullseye R01 (kernel 5.4.142)

Buster R01 (kernel 4.14.78)

Stretch R02 (kernel 4.9.88)

Stretch R01 (kernel 4.9.11)

Jessie R03 (kernel 4.1.15)

Legacy releases

Boot2Qt <rssbutton height=20 width=20></rssbutton>
Boot2Qt Dunfell (Qt 6.0.4, kernel 5.4.85)

Boot2Qt Thud (Qt 5.13.2, kernel 4.14.78)

Boot2Qt Morty (Qt 5.9.6, kernel 4.1.15)

Qt logo.png
Specs summary
CPUNXP i.MX7-Dual:
Dual 1GHz ARM Cortex™-A7,
Real-time 200MHz Cortex™-M4 co-processor
MemoryUp to 2GB DDR3L
GPU2D Pixel acceleration engine
Display24bits Parallel LCD up to WXGA (1366×768),
EPDC (E-Ink),
Resistive/capacitive touch screen
StorageSD card,
SLC NAND flash up to 512MB / eMMC up to 32GB
NetworkEthernet: 2 × 10/100/1000 Mbps,
WiFi: Certified 802.11 a/b/g/n/ac,
Bluetooth: 4.2, BLE
RTCOn carrier
CAN bus{{{can}}}
UARTsx7, up to 4 Mbps
1 × Host,
1 × OTG
AudioHeadphone, Line In/Out
Temperature Range-20 to 85°C
Dimensions38.6mm × 67.8mm

Latest News

March 2018: Critical software update: New U-Boot version with SPL support for the VAR-SOM-MX7

This critical software update allows future-proofing your software build and automatically support new DDR3 component generations which are released every 6-12 months by the vendors. The same SPL and U-Boot will automatically adapt to the new DDR3 internal timing characteristics by retrieving the required parameters stored on the on-SOM EEPROM.

Further information:

Variscite uses SPL to initialize the RAM using values it reads at runtime from the EEPROM. During production we write the appropriate init values for the RAM chip of each specific SOM on its EEPROM. This way, in the future, when a specific RAM chip gets to its end of life (for example), we can replace it with another (and write its values on the EEPROM), without having to use a different U-Boot image. So after this change customers can use the same SPL and U-Boot images on all of their boards, for the entire life time of their products, and the specific RAM chip on each SOM becomes irrelevant to them.

Affected SOMs:

All variants of the VAR-SOM-MX7


This update was already pushed to all of the Yocto and Debian branches for the VAR-SOM-MX7, and the relevant Wiki pages were updated. It is highly recommended to update to the latest commit of the branch you are using. Otherwise, please apply the appropriate patch from the following:

Yocto Rocko:
Yocto Pyro:
Yocto Morty:
Yocto Krogoth R2:
Yocto Krogoth R1:
Yocto Jethro:
Debian Stretch:
Debian Jessie R3:
Debian Jessie R2:
Debian Jessie R1:

Also, starting from May 1, 2018, Variscite will replace the default production U-Boot image that is preloaded on the SOMs, and will ship new SOMs with SPL and U-Boot preloaded on them.