DART-MX8M SPI: Difference between revisions

From Variscite Wiki
No edit summary
No edit summary
(36 intermediate revisions by 5 users not shown)
Line 1: Line 1:
{{PageHeader|DART-MX8M - SPI}} {{DocImage|category1=DART-MX8M|category2=Yocto}} __toc__
<!-- Set release according to "release" parameter in URL and use RELEASE_SUMO_V1.0_DART-MX8M as default
In this example we will show how to configure and test SPI1 on DART-MX8M. The SPI pins on external connector J16
--> {{#vardefine:RELEASE_PARAM|{{#urlget:release|RELEASE_SUMO_V1.0_DART-MX8M}}}} <!--
--> {{#lst:Yocto_Platform_Customization|{{#var:RELEASE_PARAM}}}} <!--
--> {{#lst:B2QT_Platform_Customization|{{#var:RELEASE_PARAM}}}} <!--
--> {{#lst:Android_Platform_Customization|{{#var:RELEASE_PARAM}}}} <!--
--> {{PageHeader|{{#var:HARDWARE_NAME}} SPI}} {{DocImage|category1=Yocto|category2=Android}}[[Category:Debian]][[Category:DART-MX8M]][[Category:DART-MX8M-MINI]][[Category:DART-MX8M-PLUS]]__toc__
<!-- Set local variables
-->{{#vardefine:DEFAULT_DTS|{{#replace:{{#var:DEFAULT_DTB}}|dtb|dts}}}}
 
In this example we will show how to configure and test SPI1 on {{#var:HARDWARE_NAME}}. The SPI pins on external connector J16
are used for SPI loopback test.
are used for SPI loopback test.


= Kernel configuration=
= Kernel configuration=
Verify that the i.MX SPI driver (CONFIG_SPI_IMX) is enabled in your kernel configuration:
* In menuconfig: Device Drivers -> SPI support -> <*> Freescale i.MX SPI controllers<br>
Verify that the User mode SPI driver (CONFIG_SPI_SPIDEV) is enabled in your kernel configuration:
Verify that the User mode SPI driver (CONFIG_SPI_SPIDEV) is enabled in your kernel configuration:
* In menuconfig: Device Drivers -> SPI support -> <*>   User mode SPI device driver support<br>
* In menuconfig: Device Drivers -> SPI support -> <*> User mode SPI device driver support<br>


= Device Tree configuration =
= Device Tree configuration =


The default DART-MX8M SPI configuration is for resistive touch controller on CS0.  
The default {{#var:HARDWARE_NAME}} SPI configuration is for resistive touch controller on CS0.  
For the purpose of loopback test the configuration should be modified to use different CS line.
For the purpose of loop back test the configuration should be modified to use a different CS line.
   
   
== Add spidev node ==
== Add spidev node ==
Edit arch/arm64/boot/dts/variscite/imx8m-var-dart-common.dtsi and add cs-gpios property and spidev node.<br>
{{#ifeq: {{#var:HARDWARE_NAME}} | DART-MX8M |
Edit {{#ifeq: {{#var:ANDROID_NAME}} | Pie |{{#var:BUILD_FOLDER}}/{{#var:BUILD_FOLDER_ANDROID}}/variscite/kernel_imx/}}arch/arm64/boot/dts/{{#ifeq: {{#var:YOCTO_NAME}} | Morty |variscite/imx8m-var-dart-common.dtsi|freescale/fsl-imx8mq-var-dart-common.dtsi}} to modify cs-gpios property and add spidev node.<br>
GPIO1_12 will be used in this example to control SPI CS0.
GPIO1_12 will be used in this example to control SPI CS0.


Line 20: Line 33:
#address-cells = <1>;
#address-cells = <1>;
#size-cells = <0>;
#size-cells = <0>;
num-cs = <1>;
  pinctrl-names = "default";
  pinctrl-names = "default";
pinctrl-0 = <&pinctrl_ecspi1>;
pinctrl-0 = <&pinctrl_ecspi1>;
        cs-gpios = <&gpio1 12 0>;
        fsl,spi-num-chipselects = <1>;
status = "okay";
status = "okay";
        spidev@0 {
              compatible = "spidev";
              spi-max-frequency = <12000000>;
              reg = <0>;
        };
};
</pre>
| {{#ifeq: {{#var:HARDWARE_NAME}} | DART-MX8M-MINI |
Edit {{#ifeq: {{#var:ANDROID_NAME}} | Pie |{{#var:BUILD_FOLDER}}/{{#var:BUILD_FOLDER_ANDROID}}/variscite/kernel_imx/}}/arch/arm64/boot/dts/freescale/{{#var:DEFAULT_DTS}} to modify cs-gpios property and add spidev node.<br>
GPIO1_12 will be used in this example to control SPI CS0.
<pre>
&ecspi1 {
#address-cells = <1>;
#size-cells = <0>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_ecspi1>;
        cs-gpios = <&gpio1 12 0>;
        fsl,spi-num-chipselects = <1>;
status = "okay";
        spidev@0 {
              compatible = "spidev";
              spi-max-frequency = <12000000>;
              reg = <0>;
        };
};
</pre>
| {{#ifeq: {{#var:HARDWARE_NAME}} | VAR-SOM-MX8M-NANO |
Edit {{#ifeq: {{#var:ANDROID_NAME}} | Pie |{{#var:BUILD_FOLDER}}/{{#var:BUILD_FOLDER_ANDROID}}/variscite/kernel_imx/}}/arch/arm64/boot/dts/freescale/{{#var:DEFAULT_DTS}} to modify cs-gpios property and add spidev node.<br>
GPIO1_0 will be used in this example to control SPI CS0.
<pre>
&ecspi1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_ecspi1>;
        cs-gpios = <&gpio1 0 0>;
        fsl,spi-num-chipselects = <1>;
        /delete-property/ dmas;
        /delete-property/ dma-names;
status = "okay";
        spidev@0 {
              compatible = "spidev";
              spi-max-frequency = <12000000>;
              reg = <0>;
        };
};
</pre>
| {{#ifeq: {{#var:HARDWARE_NAME}} | DART-MX8M-PLUS |
Edit {{#ifeq: {{#var:ANDROID_NAME}} | Pie |{{#var:BUILD_FOLDER}}/{{#var:BUILD_FOLDER_ANDROID}}/variscite/kernel_imx/}}/arch/arm64/boot/dts/freescale/{{#var:DEFAULT_DTS}} to modify cs-gpios property and add spidev node.<br>
GPIO1_12 will be used in this example to control SPI CS0.
<pre>
&ecspi1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_ecspi1>;
         cs-gpios = <&gpio1 12 0>;
         cs-gpios = <&gpio1 12 0>;
status = "okay";


         chip1: spidev@0 {
         spidev@0 {
               compatible = "spidev";
               compatible = "spidev";
               spi-max-frequency = <12000000>;
               spi-max-frequency = <12000000>;
Line 33: Line 106:
};
};
</pre>
</pre>
|}} }} }} }}


== Configure SPI1 pins ==
== Configure SPI1 pins ==
{{#ifeq: {{#var:HARDWARE_NAME}} | DART-MX8M |
<pre>
<pre>
&iomuxc {
&iomuxc {
imx8mq-evk {
imx8m-var-dart {
                 ...
                 ...
pinctrl_ecspi1: ecspi1grp {
pinctrl_ecspi1: ecspi1grp {
fsl,pins = <
fsl,pins = <
MX8MQ_IOMUXC_ECSPI1_SCLK_ECSPI1_SCLK 0x11
MX8MQ_IOMUXC_ECSPI1_SCLK_ECSPI1_SCLK 0x11
Line 52: Line 127:
};
};
</pre>
</pre>
| {{#ifeq: {{#var:HARDWARE_NAME}} | DART-MX8M-MINI |
<pre>
&iomuxc {
imx8mm-var-dart {
                ...
  pinctrl_ecspi1: ecspi1grp {
fsl,pins = <
MX8MM_IOMUXC_ECSPI1_SCLK_ECSPI1_SCLK 0x11
MX8MM_IOMUXC_ECSPI1_MOSI_ECSPI1_MOSI 0x11
MX8MM_IOMUXC_ECSPI1_MISO_ECSPI1_MISO 0x11
MX8MM_IOMUXC_ECSPI1_SS0_GPIO5_IO9         0x11
                                MX8MM_IOMUXC_GPIO1_IO12_GPIO1_IO12         0x11
>;
};
                ...
};
};
</pre>
| {{#ifeq: {{#var:HARDWARE_NAME}} | VAR-SOM-MX8M-NANO |
<pre>
&iomuxc {
imx8mn-var-som {
                ...
  pinctrl_ecspi1: ecspi1grp {
fsl,pins = <
                                MX8MN_IOMUXC_ECSPI1_SCLK_ECSPI1_SCLK        0x13
                                MX8MN_IOMUXC_ECSPI1_MOSI_ECSPI1_MOSI        0x13
                                MX8MN_IOMUXC_ECSPI1_MISO_ECSPI1_MISO        0x13
                                MX8MN_IOMUXC_GPIO1_IO14_GPIO1_IO14          0x13
                                MX8MN_IOMUXC_GPIO1_IO00_GPIO1_IO0          0x13
>;
};
                ...
};
};
</pre>
| {{#ifeq: {{#var:HARDWARE_NAME}} | DART-MX8M-PLUS |
<pre>
&iomuxc {
          ...
  pinctrl_ecspi1: ecspi1grp {
fsl,pins = <
MX8MP_IOMUXC_ECSPI1__SCLK_ECSPI1_SCLK 0x11
MX8MP_IOMUXC_ECSPI1__MOSI_ECSPI1_MOSI 0x11
MX8MP_IOMUXC_ECSPI1__MISO_ECSPI1_MISO 0x11
MX8MP_IOMUXC_ECSPI1__SS0_GPIO5_IO9         0x11
                                MX8MP_IOMUXC_GPIO1__IO12_GPIO1_IO12         0x11
>;
};
                ...
};
</pre>
|}} }} }} }}


= Recompile the kernel =
= Recompile the kernel =
Line 57: Line 186:


= Compile SPI test application =
= Compile SPI test application =
There's an SPI test utility in the kernel source tree: tools/spi/spidev_test.c (in older kernels: Documentation/spi/spidev_test.c)<br>
There's an SPI test utility in the kernel source tree: tools/spi/spidev_test.c<br>
To cross compile it use the following command
To cross compile it, use the following command:
<pre>
{{#ifeq: {{#var:ANDROID_NAME}} | Pie |
$ $CC ./tools/spi/spidev_test.c -o ./spidev_test
Setup the toolchain path to point to aarch64-linux-android- tools in prebuilts/gcc/linux-x86/aarch64/aarch64-linux-android-4.9/bin
</pre>
$ export ARCH=arm64
 
$ export CROSS_COMPILE={{#var:BUILD_FOLDER}}/{{#var:BUILD_FOLDER_ANDROID}}/prebuilts/gcc/linux-x86/aarch64/aarch64-linux-android-4.9/bin/aarch64-linux-android-
$ cd {{#var:BUILD_FOLDER}}/{{#var:BUILD_FOLDER_ANDROID}}/variscite/kernel_imx/tools/spi/
$ aarch64-linux-android-gcc spidev_test.c -o ./spidev_test
$ adb root
$ adb remount /system/
$ adb push spidev_test /system/bin/
|
$ $CC ./tools/spi/spidev_test.c -o ./spidev_test
}}
== SPI 1 External Connector ==
== SPI 1 External Connector ==
SPI 1 will be accessible on the following EVK pins:
SPI 1 will be accessible on the following EVK pins:
Line 71: Line 208:


= Run SPI Test =
= Run SPI Test =
Transfer spidev_test binary to DART-MX8M.<br>
Copy spidev_test binary to DART-MX8M.<br>
Loop SPI1.MOSI and SPI1.MISO by putting a jumper on J16.6 and J16.8<br>
Loop SPI1.MOSI and SPI1.MISO by putting a jumper on J16.6 and J16.8<br>
Configure GPIO5_9 (the default CS0 pin) as output with value 1 to prevent it from interfering with new CS0 pin
Configure {{#ifeq: {{#var:HARDWARE_NAME}} | VAR-SOM-MX8M-NANO | GPIO1_14 | GPIO5_9}} (the default CS0 pin) as output with value 1 to prevent it from interfering with new CS0 pin


{{#ifeq: {{#var:HARDWARE_NAME}} | VAR-SOM-MX8M-NANO |
<pre>
# echo 14 > /sys/class/gpio/export
# echo out > /sys/class/gpio/gpio14/direction
# echo 1 > /sys/class/gpio/gpio14/value
</pre>
|
<pre>
  # echo 137 > /sys/class/gpio/export  
  # echo 137 > /sys/class/gpio/export  
  # echo out > /sys/class/gpio/gpio137/direction  
  # echo out > /sys/class/gpio/gpio137/direction  
  # echo 1 > /sys/class/gpio/gpio137/value  
  # echo 1 > /sys/class/gpio/gpio137/value
</pre>
}}


Run SPI test tool
Run SPI test tool
# ./spidev_test -v -D /dev/spidev32766.0  
{{#ifeq: {{#var:YOCTO_NAME}} | Morty |
 
<pre>
# ./spidev_test -v -D /dev/spidev32766.0
</pre>
|
<pre>
# ./spidev_test -v -D /dev/spidev0.0
</pre>
}}
The output of successful test should look like this:
The output of successful test should look like this:
<pre>
<pre>
Line 91: Line 245:
</pre>
</pre>


= Using GPIOs to control SPI CS lines =
= Using multiple SPI CS lines =
The i.MX8M SPI controllers support up to 4 chip select lines. You can use GPIOs to control multiple CS lines.<br>
The i.MX8M SPI controllers support up to 4 chip select lines.<br>
In the example below GPIO1_12 and GPIO1_15 are used to control CS0 and CS1.<br>
In the example below GPIO1_12 and GPIO1_15 are used to control CS0 and CS1 respectively.<br>
When selecting CS GPIO pins make sure they are not already used to control other peripherals.
When selecting CS GPIO pins make sure they are not used to control other peripherals.


{{#ifeq: {{#var:HARDWARE_NAME}} | VAR-SOM-MX8M-NANO |
<pre>
<pre>
&ecspi1 {
&ecspi1 {
#address-cells = <1>;
#address-cells = <1>;
#size-cells = <0>;
#size-cells = <0>;
num-cs = <2>;
  pinctrl-names = "default";
  pinctrl-names = "default";
pinctrl-0 = <&pinctrl_ecspi1>;
pinctrl-0 = <&pinctrl_ecspi1>;
        cs-gpios = <&gpio1 0 0>,
                  <&gpio1 1 0>;
        fsl,spi-num-chipselects = <2>;
status = "okay";
status = "okay";
        chip1@0 {
              reg = <0>;
              ...
        };
        chip2@1 {
              reg = <1>;
              ...
        };
};
</pre>
|
<pre>
&ecspi1 {
#address-cells = <1>;
#size-cells = <0>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_ecspi1>;
         cs-gpios = <&gpio1 12 0>,
         cs-gpios = <&gpio1 12 0>,
                   <&gpio1 15 0>;
                   <&gpio1 15 0>;
        fsl,spi-num-chipselects = <2>;
status = "okay";
        chip1@0 {
              reg = <0>;
              ...
        };
        chip2@1 {
              reg = <1>;
              ...
        };
};
};
</pre>
}}


{{#ifeq: {{#var:HARDWARE_NAME}} | DART-MX8M |
<pre>
&iomuxc {
&iomuxc {
imx8mq-evk {
imx8m-var-dart {
                 ...
                 ...
pinctrl_ecspi1: ecspi1grp {
pinctrl_ecspi1: ecspi1grp {
fsl,pins = <
fsl,pins = <
MX8MQ_IOMUXC_ECSPI1_SCLK_ECSPI1_SCLK 0x11
MX8MQ_IOMUXC_ECSPI1_SCLK_ECSPI1_SCLK 0x11
Line 123: Line 315:
};
};
};
};
</pre>
</pre>
| {{#ifeq: {{#var:HARDWARE_NAME}} | DART-MX8M-MINI |
<pre>
&iomuxc {
imx8mm-var-dart {
                ...
  pinctrl_ecspi1: ecspi1grp {
fsl,pins = <
MX8MM_IOMUXC_ECSPI1_SCLK_ECSPI1_SCLK 0x11
MX8MM_IOMUXC_ECSPI1_MOSI_ECSPI1_MOSI 0x11
MX8MM_IOMUXC_ECSPI1_MISO_ECSPI1_MISO 0x11
MX8MM_IOMUXC_GPIO1_IO12_GPIO1_IO12         0x11
                                MX8MM_IOMUXC_GPIO1_I015_GPIO1_IO15         0x11
>;
};
                ...
};
};
</pre>
| {{#ifeq: {{#var:HARDWARE_NAME}} | VAR-SOM-MX8M-MINI |
<pre>
&iomuxc {
imx8mn-var-som {
                ...
  pinctrl_ecspi1: ecspi1grp {
fsl,pins = <
                                MX8MN_IOMUXC_ECSPI1_SCLK_ECSPI1_SCLK        0x13
                                MX8MN_IOMUXC_ECSPI1_MOSI_ECSPI1_MOSI        0x13
                                MX8MN_IOMUXC_ECSPI1_MISO_ECSPI1_MISO        0x13
                                MX8MN_IOMUXC_GPIO1_IO00_GPIO1_IO0          0x13
                                MX8MN_IOMUXC_GPIO1_IO00_GPIO1_IO1          0x13
>;
};
                ...
};
};
</pre>
| {{#ifeq: {{#var:HARDWARE_NAME}} | DART-MX8M-PLUS |
<pre>
&iomuxc {
                ...
  pinctrl_ecspi1: ecspi1grp {
fsl,pins = <
MX8MP_IOMUXC_ECSPI1__SCLK_ECSPI1_SCLK 0x11
MX8MP_IOMUXC_ECSPI1__MOSI_ECSPI1_MOSI 0x11
MX8MP_IOMUXC_ECSPI1__MISO_ECSPI1_MISO 0x11
MX8MP_IOMUXC_GPIO1__IO12_GPIO1_IO12         0x11
                                MX8MP_IOMUXC_GPIO1__I015_GPIO1_IO15         0x11
>;
};
                ...
};
</pre>
|}} }} }} }}

Revision as of 21:42, 29 July 2022

DART-MX8M SPI


In this example we will show how to configure and test SPI1 on DART-MX8M. The SPI pins on external connector J16 are used for SPI loopback test.

Kernel configuration

Verify that the i.MX SPI driver (CONFIG_SPI_IMX) is enabled in your kernel configuration:

  • In menuconfig: Device Drivers -> SPI support -> <*> Freescale i.MX SPI controllers

Verify that the User mode SPI driver (CONFIG_SPI_SPIDEV) is enabled in your kernel configuration:

  • In menuconfig: Device Drivers -> SPI support -> <*> User mode SPI device driver support

Device Tree configuration

The default DART-MX8M SPI configuration is for resistive touch controller on CS0. For the purpose of loop back test the configuration should be modified to use a different CS line.

Add spidev node

Edit arch/arm64/boot/dts/freescale/fsl-imx8mq-var-dart-common.dtsi to modify cs-gpios property and add spidev node.
GPIO1_12 will be used in this example to control SPI CS0.

&ecspi1 {
	#address-cells = <1>;
	#size-cells = <0>;
 	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_ecspi1>;
        cs-gpios = <&gpio1 12 0>;
        fsl,spi-num-chipselects = <1>;
	status = "okay";

        spidev@0 {
               compatible = "spidev";
               spi-max-frequency = <12000000>;
               reg = <0>;
        };
};

Configure SPI1 pins

&iomuxc {
	imx8m-var-dart {
                ...
		 pinctrl_ecspi1: ecspi1grp {
			fsl,pins = <
				MX8MQ_IOMUXC_ECSPI1_SCLK_ECSPI1_SCLK		0x11
				MX8MQ_IOMUXC_ECSPI1_MOSI_ECSPI1_MOSI		0x11
				MX8MQ_IOMUXC_ECSPI1_MISO_ECSPI1_MISO		0x11
				MX8MQ_IOMUXC_ECSPI1_SS0_GPIO5_IO9	        0x11
                                MX8MQ_IOMUXC_GPIO1_IO12_GPIO1_IO12	        0x11
			>;
		};
                ...
	};
};

Recompile the kernel

Compile the kernel (only if kernel configuration was changed) and device tree and update the SOM.

Compile SPI test application

There's an SPI test utility in the kernel source tree: tools/spi/spidev_test.c
To cross compile it, use the following command:

$ $CC ./tools/spi/spidev_test.c -o ./spidev_test

SPI 1 External Connector

SPI 1 will be accessible on the following EVK pins:

  • J16.2 - SPI1.SCLK
  • J16.4 - SPI1.SS0
  • J16.6 - SPI1.MOSI
  • J16.8 - SPI1.MISO

Run SPI Test

Copy spidev_test binary to DART-MX8M.
Loop SPI1.MOSI and SPI1.MISO by putting a jumper on J16.6 and J16.8
Configure GPIO5_9 (the default CS0 pin) as output with value 1 to prevent it from interfering with new CS0 pin

 # echo 137 > /sys/class/gpio/export 
 # echo out > /sys/class/gpio/gpio137/direction 
 # echo 1 > /sys/class/gpio/gpio137/value

Run SPI test tool

# ./spidev_test -v -D /dev/spidev0.0 

The output of successful test should look like this:

spi mode: 0x20
bits per word: 8
max speed: 500000 Hz (500 KHz)
TX | FF FF FF FF FF FF 40 00 00 00 00 95 FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF F0 0D  | ......@....�..................�.
RX | FF FF FF FF FF FF 40 00 00 00 00 95 FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF F0 0D  | ......@....�..................�.

Using multiple SPI CS lines

The i.MX8M SPI controllers support up to 4 chip select lines.
In the example below GPIO1_12 and GPIO1_15 are used to control CS0 and CS1 respectively.
When selecting CS GPIO pins make sure they are not used to control other peripherals.

&ecspi1 {
	#address-cells = <1>;
	#size-cells = <0>;
 	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_ecspi1>;
        cs-gpios = <&gpio1 12 0>,
                   <&gpio1 15 0>;
        fsl,spi-num-chipselects = <2>;
	status = "okay";

        chip1@0 {
               reg = <0>;
               ...
        };

        chip2@1 {
               reg = <1>;
               ...
        };
};
&iomuxc {
	imx8m-var-dart {
                ...
 		pinctrl_ecspi1: ecspi1grp {
			fsl,pins = <
				MX8MQ_IOMUXC_ECSPI1_SCLK_ECSPI1_SCLK		0x11
				MX8MQ_IOMUXC_ECSPI1_MOSI_ECSPI1_MOSI		0x11
				MX8MQ_IOMUXC_ECSPI1_MISO_ECSPI1_MISO		0x11
				MX8MQ_IOMUXC_GPIO1_IO12_GPIO1_IO12	        0x11
                                MX8MQ_IOMUXC_GPIO1_I015_GPIO1_IO15	        0x11
			>;
		};
                ...
	};
};