DART-MX8M SPI: Difference between revisions

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<!-- Set release according to "release" parameter in URL and use RELEASE_SUMO_V1.0_DART-MX8M as default
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--> {{#vardefine:RELEASE_PARAM|{{#urlget:release|RELEASE_SUMO_V1.0_DART-MX8M}}}} <!--
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--> {{#lst:B2QT_Platform_Customization|{{#var:RELEASE_PARAM}}}} <!--
--> {{PageHeader|{{#var:HARDWARE_NAME}} SPI}} {{DocImage|category1=Yocto|category2=Android}}[[Category:DART-MX8M]][[Category:DART-MX8M-MINI]] __toc__
--> {{#lst:Android_Platform_Customization|{{#var:RELEASE_PARAM}}}} <!--
--> {{PageHeader|{{#var:HARDWARE_NAME}} SPI}} {{DocImage|category1=Yocto|category2=Android}}[[Category:Debian]][[Category:DART-MX8M]][[Category:DART-MX8M-MINI]][[Category:DART-MX8M-PLUS]]__toc__
<!-- Set local variables
-->{{#vardefine:DEFAULT_DTS|{{#replace:{{#var:DEFAULT_DTB}}|dtb|dts}}}}
 
In this example we will show how to configure and test SPI1 on {{#var:HARDWARE_NAME}}. The SPI pins on external connector J16
In this example we will show how to configure and test SPI1 on {{#var:HARDWARE_NAME}}. The SPI pins on external connector J16
are used for SPI loopback test.
are used for SPI loopback test.
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= Device Tree configuration =
= Device Tree configuration =


The default DART-MX8M SPI configuration is for resistive touch controller on CS0.  
The default {{#var:HARDWARE_NAME}} SPI configuration is for resistive touch controller on CS0.  
For the purpose of loop back test the configuration should be modified to use different CS line.
For the purpose of loop back test the configuration should be modified to use a different CS line.
   
   
== Add spidev node ==
== Add spidev node ==
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</pre>
</pre>
| {{#ifeq: {{#var:HARDWARE_NAME}} | DART-MX8M-MINI |
| {{#ifeq: {{#var:HARDWARE_NAME}} | DART-MX8M-MINI |
Edit {{#ifeq: {{#var:ANDROID_NAME}} | Pie |{{#var:BUILD_FOLDER}}/{{#var:BUILD_FOLDER_ANDROID}}/variscite/kernel_imx/}}/arch/arm64/boot/dts/freescale/fsl-imx8mm-var-dart.dts to modify cs-gpios property and add spidev node.<br>
Edit {{#ifeq: {{#var:ANDROID_NAME}} | Pie |{{#var:BUILD_FOLDER}}/{{#var:BUILD_FOLDER_ANDROID}}/variscite/kernel_imx/}}/arch/arm64/boot/dts/freescale/{{#var:DEFAULT_DTS}} to modify cs-gpios property and add spidev node.<br>
GPIO1_12 will be used in this example to control SPI CS0.
GPIO1_12 will be used in this example to control SPI CS0.


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</pre>
</pre>
| {{#ifeq: {{#var:HARDWARE_NAME}} | VAR-SOM-MX8M-NANO |
| {{#ifeq: {{#var:HARDWARE_NAME}} | VAR-SOM-MX8M-NANO |
Edit {{#ifeq: {{#var:ANDROID_NAME}} | Pie |{{#var:BUILD_FOLDER}}/{{#var:BUILD_FOLDER_ANDROID}}/variscite/kernel_imx/}}/arch/arm64/boot/dts/freescale/fsl-imx8mn-var-som.dts to modify cs-gpios property and add spidev node.<br>
Edit {{#ifeq: {{#var:ANDROID_NAME}} | Pie |{{#var:BUILD_FOLDER}}/{{#var:BUILD_FOLDER_ANDROID}}/variscite/kernel_imx/}}/arch/arm64/boot/dts/freescale/{{#var:DEFAULT_DTS}} to modify cs-gpios property and add spidev node.<br>
GPIO1_0 will be used in this example to control SPI CS0.
GPIO1_0 will be used in this example to control SPI CS0.


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};
};
</pre>
</pre>
|}} }} }}
| {{#ifeq: {{#var:HARDWARE_NAME}} | DART-MX8M-PLUS |
Edit {{#ifeq: {{#var:ANDROID_NAME}} | Pie |{{#var:BUILD_FOLDER}}/{{#var:BUILD_FOLDER_ANDROID}}/variscite/kernel_imx/}}/arch/arm64/boot/dts/freescale/{{#var:DEFAULT_DTS}} to modify cs-gpios property and add spidev node.<br>
GPIO1_12 will be used in this example to control SPI CS0.
 
<pre>
&ecspi1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_ecspi1>;
        cs-gpios = <&gpio1 12 0>;
status = "okay";
 
        spidev@0 {
              compatible = "spidev";
              spi-max-frequency = <12000000>;
              reg = <0>;
        };
};
</pre>
|}} }} }} }}


== Configure SPI1 pins ==
== Configure SPI1 pins ==
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};
};
</pre>
</pre>
|}} }} }}
| {{#ifeq: {{#var:HARDWARE_NAME}} | DART-MX8M-PLUS |
<pre>
&iomuxc {
          ...
  pinctrl_ecspi1: ecspi1grp {
fsl,pins = <
MX8MP_IOMUXC_ECSPI1__SCLK_ECSPI1_SCLK 0x11
MX8MP_IOMUXC_ECSPI1__MOSI_ECSPI1_MOSI 0x11
MX8MP_IOMUXC_ECSPI1__MISO_ECSPI1_MISO 0x11
MX8MP_IOMUXC_ECSPI1__SS0_GPIO5_IO9         0x11
                                MX8MP_IOMUXC_GPIO1__IO12_GPIO1_IO12         0x11
>;
};
                ...
};
</pre>
 
|}} }} }} }}


= Recompile the kernel =
= Recompile the kernel =
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};
};
</pre>
</pre>
|}} }} }}
| {{#ifeq: {{#var:HARDWARE_NAME}} | DART-MX8M-PLUS |
<pre>
&iomuxc {
                ...
  pinctrl_ecspi1: ecspi1grp {
fsl,pins = <
MX8MP_IOMUXC_ECSPI1__SCLK_ECSPI1_SCLK 0x11
MX8MP_IOMUXC_ECSPI1__MOSI_ECSPI1_MOSI 0x11
MX8MP_IOMUXC_ECSPI1__MISO_ECSPI1_MISO 0x11
MX8MP_IOMUXC_GPIO1__IO12_GPIO1_IO12         0x11
                                MX8MP_IOMUXC_GPIO1__I015_GPIO1_IO15         0x11
>;
};
                ...
};
</pre>
|}} }} }} }}

Revision as of 21:42, 29 July 2022

DART-MX8M SPI


In this example we will show how to configure and test SPI1 on DART-MX8M. The SPI pins on external connector J16 are used for SPI loopback test.

Kernel configuration

Verify that the i.MX SPI driver (CONFIG_SPI_IMX) is enabled in your kernel configuration:

  • In menuconfig: Device Drivers -> SPI support -> <*> Freescale i.MX SPI controllers

Verify that the User mode SPI driver (CONFIG_SPI_SPIDEV) is enabled in your kernel configuration:

  • In menuconfig: Device Drivers -> SPI support -> <*> User mode SPI device driver support

Device Tree configuration

The default DART-MX8M SPI configuration is for resistive touch controller on CS0. For the purpose of loop back test the configuration should be modified to use a different CS line.

Add spidev node

Edit arch/arm64/boot/dts/freescale/fsl-imx8mq-var-dart-common.dtsi to modify cs-gpios property and add spidev node.
GPIO1_12 will be used in this example to control SPI CS0.

&ecspi1 {
	#address-cells = <1>;
	#size-cells = <0>;
 	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_ecspi1>;
        cs-gpios = <&gpio1 12 0>;
        fsl,spi-num-chipselects = <1>;
	status = "okay";

        spidev@0 {
               compatible = "spidev";
               spi-max-frequency = <12000000>;
               reg = <0>;
        };
};

Configure SPI1 pins

&iomuxc {
	imx8m-var-dart {
                ...
		 pinctrl_ecspi1: ecspi1grp {
			fsl,pins = <
				MX8MQ_IOMUXC_ECSPI1_SCLK_ECSPI1_SCLK		0x11
				MX8MQ_IOMUXC_ECSPI1_MOSI_ECSPI1_MOSI		0x11
				MX8MQ_IOMUXC_ECSPI1_MISO_ECSPI1_MISO		0x11
				MX8MQ_IOMUXC_ECSPI1_SS0_GPIO5_IO9	        0x11
                                MX8MQ_IOMUXC_GPIO1_IO12_GPIO1_IO12	        0x11
			>;
		};
                ...
	};
};

Recompile the kernel

Compile the kernel (only if kernel configuration was changed) and device tree and update the SOM.

Compile SPI test application

There's an SPI test utility in the kernel source tree: tools/spi/spidev_test.c
To cross compile it, use the following command:

$ $CC ./tools/spi/spidev_test.c -o ./spidev_test

SPI 1 External Connector

SPI 1 will be accessible on the following EVK pins:

  • J16.2 - SPI1.SCLK
  • J16.4 - SPI1.SS0
  • J16.6 - SPI1.MOSI
  • J16.8 - SPI1.MISO

Run SPI Test

Copy spidev_test binary to DART-MX8M.
Loop SPI1.MOSI and SPI1.MISO by putting a jumper on J16.6 and J16.8
Configure GPIO5_9 (the default CS0 pin) as output with value 1 to prevent it from interfering with new CS0 pin

 # echo 137 > /sys/class/gpio/export 
 # echo out > /sys/class/gpio/gpio137/direction 
 # echo 1 > /sys/class/gpio/gpio137/value

Run SPI test tool

# ./spidev_test -v -D /dev/spidev0.0 

The output of successful test should look like this:

spi mode: 0x20
bits per word: 8
max speed: 500000 Hz (500 KHz)
TX | FF FF FF FF FF FF 40 00 00 00 00 95 FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF F0 0D  | ......@....�..................�.
RX | FF FF FF FF FF FF 40 00 00 00 00 95 FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF F0 0D  | ......@....�..................�.

Using multiple SPI CS lines

The i.MX8M SPI controllers support up to 4 chip select lines.
In the example below GPIO1_12 and GPIO1_15 are used to control CS0 and CS1 respectively.
When selecting CS GPIO pins make sure they are not used to control other peripherals.

&ecspi1 {
	#address-cells = <1>;
	#size-cells = <0>;
 	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_ecspi1>;
        cs-gpios = <&gpio1 12 0>,
                   <&gpio1 15 0>;
        fsl,spi-num-chipselects = <2>;
	status = "okay";

        chip1@0 {
               reg = <0>;
               ...
        };

        chip2@1 {
               reg = <1>;
               ...
        };
};
&iomuxc {
	imx8m-var-dart {
                ...
 		pinctrl_ecspi1: ecspi1grp {
			fsl,pins = <
				MX8MQ_IOMUXC_ECSPI1_SCLK_ECSPI1_SCLK		0x11
				MX8MQ_IOMUXC_ECSPI1_MOSI_ECSPI1_MOSI		0x11
				MX8MQ_IOMUXC_ECSPI1_MISO_ECSPI1_MISO		0x11
				MX8MQ_IOMUXC_GPIO1_IO12_GPIO1_IO12	        0x11
                                MX8MQ_IOMUXC_GPIO1_I015_GPIO1_IO15	        0x11
			>;
		};
                ...
	};
};