SPI

Overview

In this example we show how to configure and test SPI on . The SPI pins on external connector J16 will be used used to run SPI loopback test.

Kernel configuration

Verify that the i.MX LPSPI driver (CONFIG_SPI_FSL_LPSPI) is enabled in your kernel configuration:

In menuconfig: Device Drivers -> SPI support -> <*> Freescale i.MX LPSPI controller

Verify that the User mode SPI driver (CONFIG_SPI_SPIDEV) is enabled in your kernel configuration:

In menuconfig: Device Drivers -> SPI support -> <*> User mode SPI device driver support

Check spidev node

On VAR-SOM-MX8 check that spidev node exists and is enabled in arch/arm64/boot/dts/freescale/imx8qm-var-som.dtsi.
GPIO3_24 will be used in this example to control SPI CS0.

&lpspi1 {	
	#address-cells = <1>;
	#size-cells = <0>;
	fsl,spi-num-chipselects = <1>;
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_lpspi1 &pinctrl_lpspi1_cs>;
	cs-gpios = <&gpio3 24 0>;
	status = "okay";

        spidev@0 {
		compatible = "spidev";
		spi-max-frequency = <12000000>;
		reg = <0>;
		status = "okay";	
        };
};

On SPEAR-MX8 check that spidev nodes exist and are enabled in arch/arm64/boot/dts/freescale/imx8qm-var-spear.dtsi.
GPIO3_5 and GPIO3_6 will be used in this example to control SPI CS0 and CS1 respectively.

&lpspi0 {
	#address-cells = <1>;
	#size-cells = <0>;
	fsl,spi-num-chipselects = <2>;
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_lpspi0 &pinctrl_lpspi0_cs>;
	cs-gpios = <&gpio3 5 0>,
		   <&gpio3 6 0>;
	status = "okay";

        spidev@0 {
		compatible = "spidev";
		spi-max-frequency = <12000000>;
		reg = <0>;
		status = "okay";	
        };

        spidev@1 {
		compatible = "spidev";
		spi-max-frequency = <12000000>;
		reg = <1>;
		status = "okay";	
        };
};

Check configuration of SPI pins

On VAR-SOM-MX8:

&iomuxc {
	imx8qm-var-som {
                ...
		 pinctrl_lpspi1: lpspi1grp {
			 fsl,pins = <
				SC_P_ADC_IN3_DMA_SPI1_SCK				0x0600004c
				SC_P_ADC_IN4_DMA_SPI1_SDO				0x0600004c
				SC_P_ADC_IN5_DMA_SPI1_SDI				0x0600004c
			>;
		};

		pinctrl_lpspi1_cs: lpspi1csgrp {
			fsl,pins = <
				SC_P_ADC_IN6_LSIO_GPIO3_IO24				0x00000021
			>;
		};
                ...
	};
};

On SPEAR-MX8:

&iomuxc {
	imx8qm-var-spear {
                ...
		pinctrl_lpspi0: lpspi0grp {
			fsl,pins = <
				SC_P_SPI0_SCK_DMA_SPI0_SCK			0x0600004c
				SC_P_SPI0_SDO_DMA_SPI0_SDO			0x0600004c
				SC_P_SPI0_SDI_DMA_SPI0_SDI			0x0600004c
			>;
		};

		pinctrl_lpspi0_cs: lpspics0grp {
			fsl,pins = <
				SC_P_SPI0_CS0_LSIO_GPIO3_IO05			0x00000021
				SC_P_SPI0_CS1_LSIO_GPIO3_IO06			0x00000021
			>;
		};
         };
};

Recompile the kernel

Recompile the kernel and device tree (if any changes were made to DTS and kernel configuration) and update the SOM.

Compile SPI test application

There's an SPI test utility in the kernel source tree: tools/spi/spidev_test.c
To cross compile it, use the following command:

$ $CC ./tools/spi/spidev_test.c -o ./spidev_test

SPI External Connector

On Symphony carrier board (VAR-SOM-MX8X and VAR-SOM-MX8) SPI is accessible on the following pins:

J16.2 - SCLK
J16.4 - SS0
J16.6 - MOSI
J16.8 - MISO

On SPEAR-MX8 carrier board SPI is accessible on the following pins:

J20.1 - SCLK
J20.3 - MOSI
J20.5 - MISO
J20.7 - SS0
J20.9 - SS1

Run SPI Test

Copy spidev_test binary to the SOM.
On Symphony carrier board, loop MOSI and MISO by putting a jumper on J16.6 and J16.8
On SPEAR-MX8 carrier board, loop MOSI and MISO by putting a jumper on J20.3 and J20.5

Run SPI test tool

# ./spidev_test -v -D /dev/spidev0.0

On SPEAR-MX8 CS1 can also be tested by running

# ./spidev_test -v -D /dev/spidev0.1

The output of successful test should look like this:

spi mode: 0x20
bits per word: 8
max speed: 500000 Hz (500 KHz)
TX | FF FF FF FF FF FF 40 00 00 00 00 95 FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF F0 0D  | ......@....�..................�.
RX | FF FF FF FF FF FF 40 00 00 00 00 95 FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF F0 0D  | ......@....�..................�.

MX8 SPI

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