March 2018: Critical software update: New U-Boot version with SPL support for the VAR-SOM-MX7
This critical software update allows future-proofing your software build and automatically support new DDR3 component generations which are released every 6-12 months by the vendors.
The same SPL and U-Boot will automatically adapt to the new DDR3 internal timing characteristics by retrieving the required parameters stored on the on-SOM EEPROM.
Variscite uses SPL to initialize the RAM using values it reads at runtime from the EEPROM.
During production we write the appropriate init values for the RAM chip of each specific SOM on its EEPROM.
This way, in the future, when a specific RAM chip gets to its end of life (for example), we can replace it with another (and write its values on the EEPROM), without having to use a different U-Boot image.
So after this change customers can use the same SPL and U-Boot images on all of their boards, for the entire life time of their products, and the specific RAM chip on each SOM becomes irrelevant to them.
All variants of the VAR-SOM-MX7
This update was already pushed to all of the Yocto and Debian branches for the VAR-SOM-MX7, and the relevant Wiki pages were updated.
It is highly recommended to update to the latest commit of the branch you are using.
Otherwise, please apply the appropriate patch from the following:
Yocto Krogoth R2:
Yocto Krogoth R1:
Debian Jessie R3:
Debian Jessie R2:
Debian Jessie R1:
Also, starting from May 1, 2018, Variscite will replace the default production U-Boot image that is preloaded on the SOMs, and will ship new SOMs with SPL and U-Boot preloaded on them.
The new images will be based on commit 3b5f889, from the imx_v2017.03_4.9.11_1.0.0_ga_var01 U-Boot branch: