MX8 SPI

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VAR-SOM-MX8X SPI

1 Overview

In this example we show how to configure and test SPI on VAR-SOM-MX8X. The SPI pins on external connector J16 will be used used to run SPI loopback test.

2 Kernel configuration

Verify that the i.MX LPSPI driver (CONFIG_SPI_FSL_LPSPI) is enabled in your kernel configuration:

  • In menuconfig: Device Drivers -> SPI support -> <*> Freescale i.MX LPSPI controller

Verify that the User mode SPI driver (CONFIG_SPI_SPIDEV) is enabled in your kernel configuration:

  • In menuconfig: Device Drivers -> SPI support -> <*> User mode SPI device driver support

2.1 Check spidev node

Check that spidev node exists and is enabled in arch/arm64/boot/dts/freescale/imx8qxp-var-som-common.dtsi.
GPIO1_0 will be used in this example to control SPI CS0.

&lpspi2 {
	#address-cells = <1>;
	#size-cells = <0>;
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_lpspi2 &pinctrl_lpspi2_cs>;
	cs-gpios = <&gpio1 0 GPIO_ACTIVE_LOW>;
	status = "okay";

        spidev@0 {
		compatible = "spidev";
		spi-max-frequency = <12000000>;
		reg = <0>;
		status = "disabled";	
        };
};

2.2 Check configuration of SPI pins

&iomuxc {
	imx8qxp-var-som {
                ...
		pinctrl_lpspi2: lpspi2grp {
			fsl,pins = <
				SC_P_SPI2_SCK_ADMA_SPI2_SCK			0x0600004c
				SC_P_MCLK_IN0_ADMA_SPI2_SDI			0x0600004c
				SC_P_SPI2_SDO_ADMA_SPI2_SDO			0x0600004c
			>;
		};

		pinctrl_lpspi2_cs: lpspi2csgrp {
			fsl,pins = <
				SC_P_SPI2_CS0_LSIO_GPIO1_IO00			0x21
			>;
		};
                ...
	};
};

3 Recompile the kernel

Recompile the kernel and device tree (if any changes were made to DTS and kernel configuration) and update the SOM.

4 Compile SPI test application

There's an SPI test utility in the kernel source tree: tools/spi/spidev_test.c
To cross compile it, use the following command:

$ $CC ./tools/spi/spidev_test.c -o ./spidev_test

4.1 SPI External Connector

On Symphony carrier board (VAR-SOM-MX8X and VAR-SOM-MX8) SPI is accessible on the following pins:

  • J16.2 - SCLK
  • J16.4 - SS0
  • J16.6 - MOSI
  • J16.8 - MISO


On SPEAR-MX8 carrier board SPI is accessible on the following pins:

  • J20.1 - SCLK
  • J20.3 - MOSI
  • J20.5 - MISO
  • J20.7 - SS0
  • J20.9 - SS1

5 Run SPI Test

Copy spidev_test binary to the SOM.
On Symphony carrier board, loop MOSI and MISO by putting a jumper on J16.6 and J16.8
On SPEAR-MX8 carrier board, loop MOSI and MISO by putting a jumper on J20.3 and J20.5

Run SPI test tool

# ./spidev_test -v -D /dev/spidev0.0 

On SPEAR-MX8 CS1 can also be tested by running

# ./spidev_test -v -D /dev/spidev0.1 

The output of successful test should look like this:

spi mode: 0x20
bits per word: 8
max speed: 500000 Hz (500 KHz)
TX | FF FF FF FF FF FF 40 00 00 00 00 95 FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF F0 0D  | ......@....�..................�.
RX | FF FF FF FF FF FF 40 00 00 00 00 95 FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF F0 0D  | ......@....�..................�.