MX8 SPI: Difference between revisions

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--> {{#vardefine:RELEASE_PARAM|{{#urlget:release}}}} <!--
--> {{#vardefine:RELEASE_PARAM|{{#urlget:release}}}} <!--
--> {{#lst:Yocto_Platform_Customization|{{#var:RELEASE_PARAM|RELEASE_SUMO_V1.0_VAR-SOM-MX8X}}}} <!--
--> {{#lst:Yocto_Platform_Customization|{{#var:RELEASE_PARAM|RELEASE_SUMO_V1.0_VAR-SOM-MX8X}}}} <!--
--> {{PageHeader|{{#var:HARDWARE_NAME}} SPI}} {{DocImage|category1=Yocto|category2=VAR-SOM-MX8X}}[[Category:VAR-SOM-MX8]] __toc__
--> {{PageHeader|{{#var:HARDWARE_NAME}} SPI}} {{DocImage|category1=Yocto|category2={{#var:HARDWARE_NAME}}}} __toc__
In this example we will show how to configure and test SPI1 on {{#var:HARDWARE_NAME}}. The SPI pins on external connector J16
are used for SPI loopback test.


= Kernel configuration=
= Overview =
 
In this example we show how to configure and test SPI on {{#var:HARDWARE_NAME}}.
The SPI pins on external connector J16 will be used used to run SPI loopback test.
 
= Kernel configuration =


Verify that the i.MX LPSPI driver (CONFIG_SPI_FSL_LPSPI) is enabled in your kernel configuration:
Verify that the i.MX LPSPI driver (CONFIG_SPI_FSL_LPSPI) is enabled in your kernel configuration:
Line 14: Line 17:
* In menuconfig: Device Drivers -> SPI support -> <*> User mode SPI device driver support<br>
* In menuconfig: Device Drivers -> SPI support -> <*> User mode SPI device driver support<br>


== Check spidev node ==
== Add spidev node ==
 
{{#ifeq: {{#var:HARDWARE_NAME}} | VAR-SOM-MX8X |
Check that spidev node exists and is enabled in arch/arm64/boot/dts/freescale/imx8qxp-var-som-common.dtsi.<br>
GPIO1_0 will be used in this example to control SPI CS0.
 
<pre>
&lpspi2 {
#address-cells = <1>;
#size-cells = <0>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_lpspi2 &pinctrl_lpspi2_cs>;
cs-gpios = <&gpio1 0 GPIO_ACTIVE_LOW>;
status = "okay";


Edit arch/arm64/boot/dts/{{#ifeq: {{#var:HARDWARE_NAME}} | DART-MX8M |{{#ifeq: {{#var:YOCTO_NAME}} | Morty |variscite/imx8m-var-dart-common.dtsi|freescale/fsl-imx8mq-var-dart-common.dtsi}} | freescale/fsl-imx8mm-var-dart.dts}}, modify cs-gpios property and add spidev node.<br>
        spidev@0 {
GPIO1_12 will be used in this example to control SPI CS0.
compatible = "spidev";
spi-max-frequency = <12000000>;
reg = <0>;
status = "disabled";
        };
};
</pre>
|
Check that spidev node exists and is enabled in arch/arm64/boot/dts/freescale/imx8qm-var-som.dtsi.<br>
GPIO3_24 will be used in this example to control SPI CS0.


<pre>
<pre>
&ecspi1 {
&lpspi1 {
#address-cells = <1>;
#address-cells = <1>;
#size-cells = <0>;
#size-cells = <0>;
pinctrl-names = "default";
fsl,spi-num-chipselects = <1>;
pinctrl-0 = <&pinctrl_ecspi1>;
pinctrl-names = "default";
        cs-gpios = <&gpio1 12 0>;
pinctrl-0 = <&pinctrl_lpspi1 &pinctrl_lpspi1_cs>;
        fsl,spi-num-chipselects = <1>;
cs-gpios = <&gpio3 24 0>;
status = "okay";
status = "okay";


         spidev@0 {
         spidev@0 {
              compatible = "spidev";
compatible = "spidev";
              spi-max-frequency = <12000000>;
spi-max-frequency = <12000000>;
              reg = <0>;
reg = <0>;
status = "okay";
         };
         };
};
};
</pre>
</pre>
}}


== Configure SPI1 pins ==
== Check configuration of SPI pins ==
{{#ifeq: {{#var:HARDWARE_NAME}} | DART-MX8M |
{{#ifeq: {{#var:HARDWARE_NAME}} | VAR-SOM-MX8X |
<pre>
<pre>
&iomuxc {
&iomuxc {
imx8m-var-dart {
imx8qxp-var-som {
                 ...
                 ...
pinctrl_ecspi1: ecspi1grp {
pinctrl_lpspi2: lpspi2grp {
fsl,pins = <
fsl,pins = <
MX8MQ_IOMUXC_ECSPI1_SCLK_ECSPI1_SCLK 0x11
SC_P_SPI2_SCK_ADMA_SPI2_SCK 0x0600004c
MX8MQ_IOMUXC_ECSPI1_MOSI_ECSPI1_MOSI 0x11
SC_P_MCLK_IN0_ADMA_SPI2_SDI 0x0600004c
MX8MQ_IOMUXC_ECSPI1_MISO_ECSPI1_MISO 0x11
SC_P_SPI2_SDO_ADMA_SPI2_SDO 0x0600004c
MX8MQ_IOMUXC_ECSPI1_SS0_GPIO5_IO9         0x11
>;
                                MX8MQ_IOMUXC_GPIO1_IO12_GPIO1_IO12         0x11
};
 
pinctrl_lpspi2_cs: lpspi2csgrp {
fsl,pins = <
SC_P_SPI2_CS0_LSIO_GPIO1_IO00 0x21
>;
>;
};
};
Line 60: Line 90:
<pre>
<pre>
&iomuxc {
&iomuxc {
imx8mm-var-dart {
imx8qm-var-som {
                 ...
                 ...
  pinctrl_ecspi1: ecspi1grp {
pinctrl_lpspi1: lpspi1grp {
fsl,pins = <
SC_P_ADC_IN3_DMA_SPI1_SCK 0x0600004c
SC_P_ADC_IN4_DMA_SPI1_SDO 0x0600004c
SC_P_ADC_IN5_DMA_SPI1_SDI 0x0600004c
>;
};
 
pinctrl_lpspi1_cs: lpspi1csgrp {
fsl,pins = <
fsl,pins = <
MX8MM_IOMUXC_ECSPI1_SCLK_ECSPI1_SCLK 0x11
SC_P_ADC_IN6_LSIO_GPIO3_IO24 0x00000021
MX8MM_IOMUXC_ECSPI1_MOSI_ECSPI1_MOSI 0x11
MX8MM_IOMUXC_ECSPI1_MISO_ECSPI1_MISO 0x11
MX8MM_IOMUXC_ECSPI1_SS0_GPIO5_IO9         0x11
                                MX8MM_IOMUXC_GPIO1_IO12_GPIO1_IO12         0x11
>;
>;
};
};
Line 78: Line 112:


= Recompile the kernel =
= Recompile the kernel =
Compile the kernel (only if kernel configuration was changed) and device tree and update the SOM.
Reompile the kernel and device tree (if any changes were made to DTS and kernel configuration) and update the SOM.


= Compile SPI test application =
= Compile SPI test application =
Line 87: Line 121:
</pre>
</pre>


== SPI 1 External Connector ==
== SPI External Connector ==
SPI 1 will be accessible on the following EVK pins:
SPI is accessible on the following EVK pins:
* J16.2 - SPI1.SCLK
* J16.2 - SCLK
* J16.4 - SPI1.SS0
* J16.4 - SS0
* J16.6 - SPI1.MOSI
* J16.6 - MOSI
* J16.8 - SPI1.MISO
* J16.8 - MISO


= Run SPI Test =
= Run SPI Test =
Copy spidev_test binary to DART-MX8M.<br>
Copy spidev_test binary to the SOM.<br>
Loop SPI1.MOSI and SPI1.MISO by putting a jumper on J16.6 and J16.8<br>
Loop MOSI and MISO by putting a jumper on J16.6 and J16.8<br>
Configure GPIO5_9 (the default CS0 pin) as output with value 1 to prevent it from interfering with new CS0 pin
 
# echo 137 > /sys/class/gpio/export
# echo out > /sys/class/gpio/gpio137/direction
# echo 1 > /sys/class/gpio/gpio137/value


Run SPI test tool
Run SPI test tool
{{#ifeq: {{#var:YOCTO_NAME}} | Morty |
<pre>
# ./spidev_test -v -D /dev/spidev32766.0
</pre>
|
<pre>
<pre>
# ./spidev_test -v -D /dev/spidev0.0  
# ./spidev_test -v -D /dev/spidev0.0  
</pre>
</pre>
}}
 
The output of successful test should look like this:
The output of successful test should look like this:
<pre>
<pre>
Line 121: Line 145:
RX | FF FF FF FF FF FF 40 00 00 00 00 95 FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF F0 0D  | ......@....�..................�.
RX | FF FF FF FF FF FF 40 00 00 00 00 95 FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF F0 0D  | ......@....�..................�.
</pre>
</pre>
= Using multiple SPI CS lines =
The i.MX8M SPI controllers support up to 4 chip select lines.<br>
In the example below GPIO1_12 and GPIO1_15 are used to control CS0 and CS1 respectively.<br>
When selecting CS GPIO pins make sure they are not used to control other peripherals.
<pre>
&ecspi1 {
#address-cells = <1>;
#size-cells = <0>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_ecspi1>;
        cs-gpios = <&gpio1 12 0>,
                  <&gpio1 15 0>;
        fsl,spi-num-chipselects = <2>;
status = "okay";
        chip1@0 {
              reg = <0>;
              ...
        };
        chip2@1 {
              reg = <1>;
              ...
        };
};
</pre>
{{#ifeq: {{#var:HARDWARE_NAME}} | DART-MX8M |
<pre>
&iomuxc {
imx8m-var-dart {
                ...
pinctrl_ecspi1: ecspi1grp {
fsl,pins = <
MX8MQ_IOMUXC_ECSPI1_SCLK_ECSPI1_SCLK 0x11
MX8MQ_IOMUXC_ECSPI1_MOSI_ECSPI1_MOSI 0x11
MX8MQ_IOMUXC_ECSPI1_MISO_ECSPI1_MISO 0x11
MX8MQ_IOMUXC_GPIO1_IO12_GPIO1_IO12         0x11
                                MX8MQ_IOMUXC_GPIO1_I015_GPIO1_IO15         0x11
>;
};
                ...
};
};
</pre>
|
<pre>
&iomuxc {
imx8mm-var-dart {
                ...
  pinctrl_ecspi1: ecspi1grp {
fsl,pins = <
MX8MM_IOMUXC_ECSPI1_SCLK_ECSPI1_SCLK 0x11
MX8MM_IOMUXC_ECSPI1_MOSI_ECSPI1_MOSI 0x11
MX8MM_IOMUXC_ECSPI1_MISO_ECSPI1_MISO 0x11
MX8MM_IOMUXC_GPIO1_IO12_GPIO1_IO12         0x11
                                MX8MM_IOMUXC_GPIO1_I015_GPIO1_IO15         0x11
>;
};
                ...
};
};
</pre>
}}

Revision as of 17:33, 2 September 2019

VAR-SOM-MX8X SPI

Overview

In this example we show how to configure and test SPI on VAR-SOM-MX8X. The SPI pins on external connector J16 will be used used to run SPI loopback test.

Kernel configuration

Verify that the i.MX LPSPI driver (CONFIG_SPI_FSL_LPSPI) is enabled in your kernel configuration:

  • In menuconfig: Device Drivers -> SPI support -> <*> Freescale i.MX LPSPI controller

Verify that the User mode SPI driver (CONFIG_SPI_SPIDEV) is enabled in your kernel configuration:

  • In menuconfig: Device Drivers -> SPI support -> <*> User mode SPI device driver support

Check spidev node

Check that spidev node exists and is enabled in arch/arm64/boot/dts/freescale/imx8qxp-var-som-common.dtsi.
GPIO1_0 will be used in this example to control SPI CS0.

&lpspi2 {
	#address-cells = <1>;
	#size-cells = <0>;
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_lpspi2 &pinctrl_lpspi2_cs>;
	cs-gpios = <&gpio1 0 GPIO_ACTIVE_LOW>;
	status = "okay";

        spidev@0 {
		compatible = "spidev";
		spi-max-frequency = <12000000>;
		reg = <0>;
		status = "disabled";	
        };
};

Check configuration of SPI pins

&iomuxc {
	imx8qxp-var-som {
                ...
		pinctrl_lpspi2: lpspi2grp {
			fsl,pins = <
				SC_P_SPI2_SCK_ADMA_SPI2_SCK			0x0600004c
				SC_P_MCLK_IN0_ADMA_SPI2_SDI			0x0600004c
				SC_P_SPI2_SDO_ADMA_SPI2_SDO			0x0600004c
			>;
		};

		pinctrl_lpspi2_cs: lpspi2csgrp {
			fsl,pins = <
				SC_P_SPI2_CS0_LSIO_GPIO1_IO00			0x21
			>;
		};
                ...
	};
};

Recompile the kernel

Reompile the kernel and device tree (if any changes were made to DTS and kernel configuration) and update the SOM.

Compile SPI test application

There's an SPI test utility in the kernel source tree: tools/spi/spidev_test.c
To cross compile it, use the following command:

$ $CC ./tools/spi/spidev_test.c -o ./spidev_test

SPI External Connector

SPI is accessible on the following EVK pins:

  • J16.2 - SCLK
  • J16.4 - SS0
  • J16.6 - MOSI
  • J16.8 - MISO

Run SPI Test

Copy spidev_test binary to the SOM.
Loop MOSI and MISO by putting a jumper on J16.6 and J16.8

Run SPI test tool

# ./spidev_test -v -D /dev/spidev0.0 

The output of successful test should look like this:

spi mode: 0x20
bits per word: 8
max speed: 500000 Hz (500 KHz)
TX | FF FF FF FF FF FF 40 00 00 00 00 95 FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF F0 0D  | ......@....�..................�.
RX | FF FF FF FF FF FF 40 00 00 00 00 95 FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF F0 0D  | ......@....�..................�.