MX8 SPI: Difference between revisions

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<!-- Set release according to "release" parameter in URL and use RELEASE_SUMO_V1.0_VAR-SOM-MX8X as default
<!-- Set release according to "release" parameter in URL and use RELEASE_SUMO_V1.1_VAR-SOM-MX8 as default
--> {{#vardefine:RELEASE_PARAM|{{#urlget:release}}}} <!--
--> {{INIT_RELEASE_PARAM|RELEASE_SUMO_V1.1_VAR-SOM-MX8}} <!--
--> {{#lst:Yocto_Platform_Customization|{{#var:RELEASE_PARAM|RELEASE_SUMO_V1.0_VAR-SOM-MX8X}}}} <!--
--> {{#lst:Yocto_Platform_Customization|{{#var:RELEASE_PARAM}}}} <!--
--> {{PageHeader|{{#var:HARDWARE_NAME}} SPI}} {{DocImage|category1=Yocto|category2=VAR-SOM-MX8X}}[[Category:VAR-SOM-MX8]] __toc__
--> {{#lst:Debian_Platform_Customization|{{#var:RELEASE_PARAM}}}} <!--
In this example we will show how to configure and test SPI1 on {{#var:HARDWARE_NAME}}. The SPI pins on external connector J16
--> {{PageHeader|{{#var:HARDWARE_NAME}} SPI}} {{DocImage|category1=Yocto|category2=Debian}} [[category:{{#var:HARDWARE_NAME}}]] __toc__
are used for SPI loopback test.


= Kernel configuration=
= Overview =
 
In this example we show how to configure and test SPI on {{#var:HARDWARE_NAME}}.
The SPI pins on external connector J16 will be used used to run SPI loopback test.
 
= Kernel configuration =


Verify that the i.MX LPSPI driver (CONFIG_SPI_FSL_LPSPI) is enabled in your kernel configuration:
Verify that the i.MX LPSPI driver (CONFIG_SPI_FSL_LPSPI) is enabled in your kernel configuration:
Line 14: Line 18:
* In menuconfig: Device Drivers -> SPI support -> <*> User mode SPI device driver support<br>
* In menuconfig: Device Drivers -> SPI support -> <*> User mode SPI device driver support<br>


== Check spidev node ==
== Add spidev node ==
 
{{#ifeq: {{#var:HARDWARE_NAME}} | VAR-SOM-MX8X |
Check that spidev node exists and is enabled in arch/arm64/boot/dts/freescale/imx8qxp-var-som-common.dtsi.<br>
GPIO1_0 will be used in this example to control SPI CS0.
 
<pre>
&lpspi2 {
#address-cells = <1>;
#size-cells = <0>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_lpspi2 &pinctrl_lpspi2_cs>;
cs-gpios = <&gpio1 0 GPIO_ACTIVE_LOW>;
status = "okay";
 
        spidev@0 {
compatible = "spidev";
spi-max-frequency = <12000000>;
reg = <0>;
status = "disabled";
        };
};
</pre>
|
On VAR-SOM-MX8 check that spidev node exists and is enabled in arch/arm64/boot/dts/freescale/imx8qm-var-som.dtsi.<br>
GPIO3_24 will be used in this example to control SPI CS0.
 
<pre>
&lpspi1 {
#address-cells = <1>;
#size-cells = <0>;
fsl,spi-num-chipselects = <1>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_lpspi1 &pinctrl_lpspi1_cs>;
cs-gpios = <&gpio3 24 0>;
status = "okay";


Edit arch/arm64/boot/dts/{{#ifeq: {{#var:HARDWARE_NAME}} | DART-MX8M |{{#ifeq: {{#var:YOCTO_NAME}} | Morty |variscite/imx8m-var-dart-common.dtsi|freescale/fsl-imx8mq-var-dart-common.dtsi}} | freescale/fsl-imx8mm-var-dart.dts}}, modify cs-gpios property and add spidev node.<br>
        spidev@0 {
GPIO1_12 will be used in this example to control SPI CS0.
compatible = "spidev";
spi-max-frequency = <12000000>;
reg = <0>;
status = "okay";
        };
};
</pre>


<br> On SPEAR-MX8 check that spidev nodes exist and are enabled in arch/arm64/boot/dts/freescale/imx8qm-var-spear.dtsi.<br>
GPIO3_5 and GPIO3_6 will be used in this example to control SPI CS0 and CS1 respectively.
<pre>
<pre>
&ecspi1 {
&lpspi0 {
#address-cells = <1>;
#address-cells = <1>;
#size-cells = <0>;
#size-cells = <0>;
pinctrl-names = "default";
fsl,spi-num-chipselects = <2>;
pinctrl-0 = <&pinctrl_ecspi1>;
pinctrl-names = "default";
        cs-gpios = <&gpio1 12 0>;
pinctrl-0 = <&pinctrl_lpspi0 &pinctrl_lpspi0_cs>;
        fsl,spi-num-chipselects = <1>;
cs-gpios = <&gpio3 5 0>,
  <&gpio3 6 0>;
status = "okay";
status = "okay";


         spidev@0 {
         spidev@0 {
              compatible = "spidev";
compatible = "spidev";
              spi-max-frequency = <12000000>;
spi-max-frequency = <12000000>;
              reg = <0>;
reg = <0>;
status = "okay";
        };
 
        spidev@1 {
compatible = "spidev";
spi-max-frequency = <12000000>;
reg = <1>;
status = "okay";
         };
         };
};
};
</pre>
</pre>
}}


== Configure SPI1 pins ==
== Check configuration of SPI pins ==
{{#ifeq: {{#var:HARDWARE_NAME}} | DART-MX8M |
{{#ifeq: {{#var:HARDWARE_NAME}} | VAR-SOM-MX8X |
<pre>
<pre>
&iomuxc {
&iomuxc {
imx8m-var-dart {
imx8qxp-var-som {
                 ...
                 ...
pinctrl_ecspi1: ecspi1grp {
pinctrl_lpspi2: lpspi2grp {
fsl,pins = <
fsl,pins = <
MX8MQ_IOMUXC_ECSPI1_SCLK_ECSPI1_SCLK 0x11
SC_P_SPI2_SCK_ADMA_SPI2_SCK 0x0600004c
MX8MQ_IOMUXC_ECSPI1_MOSI_ECSPI1_MOSI 0x11
SC_P_MCLK_IN0_ADMA_SPI2_SDI 0x0600004c
MX8MQ_IOMUXC_ECSPI1_MISO_ECSPI1_MISO 0x11
SC_P_SPI2_SDO_ADMA_SPI2_SDO 0x0600004c
MX8MQ_IOMUXC_ECSPI1_SS0_GPIO5_IO9         0x11
>;
                                MX8MQ_IOMUXC_GPIO1_IO12_GPIO1_IO12         0x11
};
 
pinctrl_lpspi2_cs: lpspi2csgrp {
fsl,pins = <
SC_P_SPI2_CS0_LSIO_GPIO1_IO00 0x21
>;
>;
};
};
Line 58: Line 118:
</pre>
</pre>
|
|
<br>On VAR-SOM-MX8:
<pre>
<pre>
&iomuxc {
&iomuxc {
imx8mm-var-dart {
imx8qm-var-som {
                 ...
                 ...
  pinctrl_ecspi1: ecspi1grp {
pinctrl_lpspi1: lpspi1grp {
fsl,pins = <
SC_P_ADC_IN3_DMA_SPI1_SCK 0x0600004c
SC_P_ADC_IN4_DMA_SPI1_SDO 0x0600004c
SC_P_ADC_IN5_DMA_SPI1_SDI 0x0600004c
>;
};
 
pinctrl_lpspi1_cs: lpspi1csgrp {
fsl,pins = <
fsl,pins = <
MX8MM_IOMUXC_ECSPI1_SCLK_ECSPI1_SCLK 0x11
SC_P_ADC_IN6_LSIO_GPIO3_IO24 0x00000021
MX8MM_IOMUXC_ECSPI1_MOSI_ECSPI1_MOSI 0x11
MX8MM_IOMUXC_ECSPI1_MISO_ECSPI1_MISO 0x11
MX8MM_IOMUXC_ECSPI1_SS0_GPIO5_IO9         0x11
                                MX8MM_IOMUXC_GPIO1_IO12_GPIO1_IO12         0x11
>;
>;
};
};
                 ...
                 ...
};
};
};
</pre>
<br>On SPEAR-MX8:
<pre>
&iomuxc {
imx8qm-var-spear {
                ...
pinctrl_lpspi0: lpspi0grp {
fsl,pins = <
SC_P_SPI0_SCK_DMA_SPI0_SCK 0x0600004c
SC_P_SPI0_SDO_DMA_SPI0_SDO 0x0600004c
SC_P_SPI0_SDI_DMA_SPI0_SDI 0x0600004c
>;
};
pinctrl_lpspi0_cs: lpspics0grp {
fsl,pins = <
SC_P_SPI0_CS0_LSIO_GPIO3_IO05 0x00000021
SC_P_SPI0_CS1_LSIO_GPIO3_IO06 0x00000021
>;
};
        };
};
};
</pre>
</pre>
Line 78: Line 166:


= Recompile the kernel =
= Recompile the kernel =
Compile the kernel (only if kernel configuration was changed) and device tree and update the SOM.
Recompile the kernel and device tree (if any changes were made to DTS and kernel configuration) and update the SOM.


= Compile SPI test application =
= Compile SPI test application =
Line 87: Line 175:
</pre>
</pre>


== SPI 1 External Connector ==
== SPI External Connector ==
SPI 1 will be accessible on the following EVK pins:
On Symphony carrier board (VAR-SOM-MX8X and VAR-SOM-MX8) SPI is accessible on the following pins:
* J16.2 - SPI1.SCLK
* J16.2 - SCLK
* J16.4 - SPI1.SS0
* J16.4 - SS0
* J16.6 - SPI1.MOSI
* J16.6 - MOSI
* J16.8 - SPI1.MISO
* J16.8 - MISO
 
<br>On SPEAR-MX8 carrier board SPI is accessible on the following pins:
* J20.1 - SCLK
* J20.3 - MOSI
* J20.5 - MISO
* J20.7 - SS0
* J20.9 - SS1


= Run SPI Test =
= Run SPI Test =
Copy spidev_test binary to DART-MX8M.<br>
Copy spidev_test binary to the SOM.<br>
Loop SPI1.MOSI and SPI1.MISO by putting a jumper on J16.6 and J16.8<br>
On Symphony carrier board, loop MOSI and MISO by putting a jumper on J16.6 and J16.8<br>
Configure GPIO5_9 (the default CS0 pin) as output with value 1 to prevent it from interfering with new CS0 pin
On SPEAR-MX8 carrier board, loop MOSI and MISO by putting a jumper on J20.3 and J20.5<br>
 
# echo 137 > /sys/class/gpio/export
# echo out > /sys/class/gpio/gpio137/direction
# echo 1 > /sys/class/gpio/gpio137/value


Run SPI test tool
Run SPI test tool
{{#ifeq: {{#var:YOCTO_NAME}} | Morty |
<pre>
<pre>
# ./spidev_test -v -D /dev/spidev32766.0
# ./spidev_test -v -D /dev/spidev0.0  
</pre>
</pre>
|
 
On SPEAR-MX8 CS1 can also be tested by running
<pre>
<pre>
# ./spidev_test -v -D /dev/spidev0.0
# ./spidev_test -v -D /dev/spidev0.1
</pre>
</pre>
}}
 
The output of successful test should look like this:
The output of successful test should look like this:
<pre>
<pre>
Line 121: Line 212:
RX | FF FF FF FF FF FF 40 00 00 00 00 95 FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF F0 0D  | ......@....�..................�.
RX | FF FF FF FF FF FF 40 00 00 00 00 95 FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF F0 0D  | ......@....�..................�.
</pre>
</pre>
= Using multiple SPI CS lines =
The i.MX8M SPI controllers support up to 4 chip select lines.<br>
In the example below GPIO1_12 and GPIO1_15 are used to control CS0 and CS1 respectively.<br>
When selecting CS GPIO pins make sure they are not used to control other peripherals.
<pre>
&ecspi1 {
#address-cells = <1>;
#size-cells = <0>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_ecspi1>;
        cs-gpios = <&gpio1 12 0>,
                  <&gpio1 15 0>;
        fsl,spi-num-chipselects = <2>;
status = "okay";
        chip1@0 {
              reg = <0>;
              ...
        };
        chip2@1 {
              reg = <1>;
              ...
        };
};
</pre>
{{#ifeq: {{#var:HARDWARE_NAME}} | DART-MX8M |
<pre>
&iomuxc {
imx8m-var-dart {
                ...
pinctrl_ecspi1: ecspi1grp {
fsl,pins = <
MX8MQ_IOMUXC_ECSPI1_SCLK_ECSPI1_SCLK 0x11
MX8MQ_IOMUXC_ECSPI1_MOSI_ECSPI1_MOSI 0x11
MX8MQ_IOMUXC_ECSPI1_MISO_ECSPI1_MISO 0x11
MX8MQ_IOMUXC_GPIO1_IO12_GPIO1_IO12         0x11
                                MX8MQ_IOMUXC_GPIO1_I015_GPIO1_IO15         0x11
>;
};
                ...
};
};
</pre>
|
<pre>
&iomuxc {
imx8mm-var-dart {
                ...
  pinctrl_ecspi1: ecspi1grp {
fsl,pins = <
MX8MM_IOMUXC_ECSPI1_SCLK_ECSPI1_SCLK 0x11
MX8MM_IOMUXC_ECSPI1_MOSI_ECSPI1_MOSI 0x11
MX8MM_IOMUXC_ECSPI1_MISO_ECSPI1_MISO 0x11
MX8MM_IOMUXC_GPIO1_IO12_GPIO1_IO12         0x11
                                MX8MM_IOMUXC_GPIO1_I015_GPIO1_IO15         0x11
>;
};
                ...
};
};
</pre>
}}

Latest revision as of 15:20, 6 June 2023

Warning: This page is designed to be used with a 'release' URL parameter.

This page is using the default release RELEASE_SUMO_V1.1_VAR-SOM-MX8.
To view this page for a specific Variscite SoM and software release, please follow these steps:

  1. Visit variwiki.com
  2. Select your SoM
  3. Select the software release
VAR-SOM-MX8 SPI

Overview

In this example we show how to configure and test SPI on VAR-SOM-MX8. The SPI pins on external connector J16 will be used used to run SPI loopback test.

Kernel configuration

Verify that the i.MX LPSPI driver (CONFIG_SPI_FSL_LPSPI) is enabled in your kernel configuration:

  • In menuconfig: Device Drivers -> SPI support -> <*> Freescale i.MX LPSPI controller

Verify that the User mode SPI driver (CONFIG_SPI_SPIDEV) is enabled in your kernel configuration:

  • In menuconfig: Device Drivers -> SPI support -> <*> User mode SPI device driver support

Check spidev node

On VAR-SOM-MX8 check that spidev node exists and is enabled in arch/arm64/boot/dts/freescale/imx8qm-var-som.dtsi.
GPIO3_24 will be used in this example to control SPI CS0.

&lpspi1 {	
	#address-cells = <1>;
	#size-cells = <0>;
	fsl,spi-num-chipselects = <1>;
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_lpspi1 &pinctrl_lpspi1_cs>;
	cs-gpios = <&gpio3 24 0>;
	status = "okay";

        spidev@0 {
		compatible = "spidev";
		spi-max-frequency = <12000000>;
		reg = <0>;
		status = "okay";	
        };
};


On SPEAR-MX8 check that spidev nodes exist and are enabled in arch/arm64/boot/dts/freescale/imx8qm-var-spear.dtsi.
GPIO3_5 and GPIO3_6 will be used in this example to control SPI CS0 and CS1 respectively.

&lpspi0 {
	#address-cells = <1>;
	#size-cells = <0>;
	fsl,spi-num-chipselects = <2>;
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_lpspi0 &pinctrl_lpspi0_cs>;
	cs-gpios = <&gpio3 5 0>,
		   <&gpio3 6 0>;
	status = "okay";

        spidev@0 {
		compatible = "spidev";
		spi-max-frequency = <12000000>;
		reg = <0>;
		status = "okay";	
        };

        spidev@1 {
		compatible = "spidev";
		spi-max-frequency = <12000000>;
		reg = <1>;
		status = "okay";	
        };
};

Check configuration of SPI pins


On VAR-SOM-MX8:

&iomuxc {
	imx8qm-var-som {
                ...
		 pinctrl_lpspi1: lpspi1grp {
			 fsl,pins = <
				SC_P_ADC_IN3_DMA_SPI1_SCK				0x0600004c
				SC_P_ADC_IN4_DMA_SPI1_SDO				0x0600004c
				SC_P_ADC_IN5_DMA_SPI1_SDI				0x0600004c
			>;
		};

		pinctrl_lpspi1_cs: lpspi1csgrp {
			fsl,pins = <
				SC_P_ADC_IN6_LSIO_GPIO3_IO24				0x00000021
			>;
		};
                ...
	};
};


On SPEAR-MX8:

&iomuxc {
	imx8qm-var-spear {
                ...
		pinctrl_lpspi0: lpspi0grp {
			fsl,pins = <
				SC_P_SPI0_SCK_DMA_SPI0_SCK			0x0600004c
				SC_P_SPI0_SDO_DMA_SPI0_SDO			0x0600004c
				SC_P_SPI0_SDI_DMA_SPI0_SDI			0x0600004c
			>;
		};

		pinctrl_lpspi0_cs: lpspics0grp {
			fsl,pins = <
				SC_P_SPI0_CS0_LSIO_GPIO3_IO05			0x00000021
				SC_P_SPI0_CS1_LSIO_GPIO3_IO06			0x00000021
			>;
		};
         };
};

Recompile the kernel

Recompile the kernel and device tree (if any changes were made to DTS and kernel configuration) and update the SOM.

Compile SPI test application

There's an SPI test utility in the kernel source tree: tools/spi/spidev_test.c
To cross compile it, use the following command:

$ $CC ./tools/spi/spidev_test.c -o ./spidev_test

SPI External Connector

On Symphony carrier board (VAR-SOM-MX8X and VAR-SOM-MX8) SPI is accessible on the following pins:

  • J16.2 - SCLK
  • J16.4 - SS0
  • J16.6 - MOSI
  • J16.8 - MISO


On SPEAR-MX8 carrier board SPI is accessible on the following pins:

  • J20.1 - SCLK
  • J20.3 - MOSI
  • J20.5 - MISO
  • J20.7 - SS0
  • J20.9 - SS1

Run SPI Test

Copy spidev_test binary to the SOM.
On Symphony carrier board, loop MOSI and MISO by putting a jumper on J16.6 and J16.8
On SPEAR-MX8 carrier board, loop MOSI and MISO by putting a jumper on J20.3 and J20.5

Run SPI test tool

# ./spidev_test -v -D /dev/spidev0.0 

On SPEAR-MX8 CS1 can also be tested by running

# ./spidev_test -v -D /dev/spidev0.1 

The output of successful test should look like this:

spi mode: 0x20
bits per word: 8
max speed: 500000 Hz (500 KHz)
TX | FF FF FF FF FF FF 40 00 00 00 00 95 FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF F0 0D  | ......@....�..................�.
RX | FF FF FF FF FF FF 40 00 00 00 00 95 FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF F0 0D  | ......@....�..................�.